Add Digilent Nexys 4 DDR board #43
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Looks great, and thank you for taking care to reuse existing Resources!
Apart from the minor issue with the accelerometer, do you think you could adjust the formatting to (a) consistently wrap subsignals and keyword arguments past the first line, and (b) indent the second and further lines in a resource definition by 4 spaces? Similar to versa_ecp5. This isn't a blocker for merging though, just a wish.
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New commit available, please let me know what you think about it. Thanks for reviewing. |
nmigen_boards/nexys4ddr.py
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| attrs=Attrs(IOSTANDARD="LVCMOS33")), | ||
| Resource("accelerometer_int", 0, | ||
| Pins("B13 C16", dir="i"), | ||
| Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")), |
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Could you merge these two resources into one manually-defined one, similarly to how you tackled temp_sensor below?
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Yes I'will do that
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Thank you! |
Tested succesfully on the actual board with blinky and an UART demo with flow control.
The others resources are based on the official XDC (and schematic for the DDR2), but not tested.