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base repository: azonenberg/starshipraider
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head repository: azonenberg/starshipraider
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compare: db3574ad8286
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Mar 27, 2020

  1. Copy the full SHA
    db3574a View commit details
Original file line number Diff line number Diff line change
@@ -132,12 +132,12 @@ X GND PAD -100 1500 100 R 50 50 1 1 W
X VINB_N 15 -100 100 100 R 50 50 2 1 I
X VINB_P 16 -100 200 100 R 50 50 2 1 I
X PWUPB 17 -100 400 100 R 50 50 2 1 I
X VCMB 18 1150 400 100 L 50 50 2 1 B
X VCMB 18 1150 400 100 L 50 50 2 1 P
X VOUTB_N 21 1150 100 100 L 50 50 2 1 O
X VOUTB_P 22 1150 200 100 L 50 50 2 1 O
X VOUTA_P 29 1150 200 100 L 50 50 3 1 O
X VOUTA_N 30 1150 100 100 L 50 50 3 1 O
X VCMA 33 1150 400 100 L 50 50 3 1 B
X VCMA 33 1150 400 100 L 50 50 3 1 P
X PWUPA 34 -100 400 100 R 50 50 3 1 I
X VINA_P 35 -100 200 100 R 50 50 3 1 I
X VINA_N 36 -100 100 100 R 50 50 3 1 I
@@ -165,9 +165,9 @@ P 2 0 0 0 650 200 750 200 N
P 2 0 0 0 650 600 750 600 N
P 4 0 0 0 350 350 350 50 650 200 350 350 N
P 4 0 0 0 350 750 350 450 650 600 350 750 N
X OUTA A1 1050 650 200 L 50 50 1 1 O
X OUTA A1 1050 650 200 L 50 50 1 1 C
X VDD A2 -200 950 200 R 50 50 1 1 W
X OUTB A3 1050 250 200 L 50 50 1 1 O
X OUTB A3 1050 250 200 L 50 50 1 1 C
X A_N B1 -200 550 200 R 50 50 1 1 I
X B_N B3 -200 150 200 R 50 50 1 1 I
X A_P C1 -200 650 200 R 50 50 1 1 I
@@ -193,7 +193,7 @@ P 2 0 0 0 650 150 500 150 N
P 2 0 0 0 650 250 500 250 N
P 4 0 0 0 300 350 300 50 600 200 300 350 N
X IN_N 1 -200 150 200 R 50 50 1 1 I
X VCM 2 1050 650 200 L 50 50 1 1 W
X VCM 2 1050 650 200 L 50 50 1 1 I
X V+ 3 -200 750 200 R 50 50 1 1 W
X Q_P 4 1050 250 200 L 50 50 1 1 O
X Q_N 5 1050 150 200 L 50 50 1 1 O
@@ -393,24 +393,6 @@ X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# device_Fuse
#
DEF device_Fuse F 0 0 N Y 1 F N
F0 "F" 80 0 50 V V C CNN
F1 "device_Fuse" -75 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*Fuse*
$ENDFPLIST
DRAW
S -30 -100 30 100 0 1 10 N
P 2 0 1 0 0 100 0 -100 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# device_L
#
DEF device_L L 0 40 N N 1 F N
@@ -505,6 +487,21 @@ X P3 3 -350 -100 250 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# power-azonenberg_FUSE_PWROUT
#
DEF power-azonenberg_FUSE_PWROUT F 0 10 Y Y 1 F N
F0 "F" 100 50 50 H V C CNN
F1 "power-azonenberg_FUSE_PWROUT" -100 -50 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A -75 0 75 1 1799 0 1 0 N 0 0 -150 0
A 75 0 75 -1799 -1 0 1 0 N 0 0 150 0
X ~ 1 -250 0 100 R 40 40 1 1 W
X ~ 2 250 0 100 L 40 40 1 1 w
ENDDRAW
ENDDEF
#
# power-azonenberg_LT3042
#
DEF power-azonenberg_LT3042 U 0 40 Y Y 1 F N
@@ -586,7 +583,7 @@ X SS 4 -100 50 100 R 50 50 1 1 P
X GND 5 -100 350 100 R 50 50 1 1 W
X SW 6 650 750 100 L 50 50 1 1 w
X SW 7 650 650 100 L 50 50 1 1 W
X VBST 7 650 50 100 L 50 50 1 1 w
X VBST 8 650 50 100 L 50 50 1 1 w
X VIN 9 -100 650 100 R 50 50 1 1 W
X GND PAD -100 450 100 R 50 50 1 1 W
ENDDRAW
2 changes: 1 addition & 1 deletion boards/entry-afe-characterization/gainstage.sch
Original file line number Diff line number Diff line change
@@ -409,7 +409,7 @@ SPI_SCLK
Wire Wire Line
4300 4500 4050 4500
Text Notes 4300 4700 0 50 ~ 0
SPI interace runs at 5V levels
SPI interface runs at 5V levels
Text HLabel 4300 4000 2 50 Input ~ 0
VGA_PERF_MODE
Wire Wire Line
34 changes: 17 additions & 17 deletions boards/entry-afe-characterization/psu.sch
Original file line number Diff line number Diff line change
@@ -40,21 +40,6 @@ F 3 "" H 900 900 60 0000 C CNN
-1 0 0 -1
$EndComp
NoConn ~ 1250 1000
$Comp
L device:Fuse F1
U 1 1 5E811BC3
P 1600 800
F 0 "F1" V 1403 800 50 0000 C CNN
F 1 "1A" V 1494 800 50 0000 C CNN
F 2 "" V 1530 800 50 0001 C CNN
F 3 "" H 1600 800 50 0001 C CNN
1 1600 800
0 1 1 0
$EndComp
Wire Wire Line
1450 800 1250 800
Wire Wire Line
1750 800 1950 800
Text HLabel 3650 5550 2 50 Output ~ 0
6V0_P
Text HLabel 6700 3300 2 50 Output ~ 0
@@ -1271,8 +1256,8 @@ Wire Wire Line
Connection ~ 2950 4400
Text Label 3300 4700 0 50 ~ 0
GND
Text Notes 2200 5250 0 50 ~ 0
Parallel U9/U16 for increased current
Text Notes 2950 5350 0 50 ~ 0
Parallel U9/U16 for increased current.\nThis is supported per datasheet pages\n19-20. ERC warning about power\noutputs connected together can be\nsafely ignored.
Text Label 5450 7500 2 50 ~ 0
5V0_N
$Comp
@@ -1431,4 +1416,19 @@ Wire Wire Line
Wire Wire Line
10200 5150 8600 5150
Connection ~ 8600 5150
$Comp
L power-azonenberg:FUSE_PWROUT F1
U 1 1 5E9EE5E6
P 1600 800
F 0 "F1" H 1600 1040 50 0000 C CNN
F 1 "1A" H 1600 949 50 0000 C CNN
F 2 "" H 1600 800 60 0000 C CNN
F 3 "" H 1600 800 60 0000 C CNN
1 1600 800
1 0 0 -1
$EndComp
Wire Wire Line
1250 800 1350 800
Wire Wire Line
1850 800 1950 800
$EndSCHEMATC
95 changes: 95 additions & 0 deletions boards/entry-afe-characterization/schematic-checklist.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,95 @@
# Schematic review checklist

## General

* [x] CAD ERC 100% clean. If some errors are invalid due to toolchain quirks, each exception must be inspected and signed
off as invalid.
* [x] Verify pin numbers of all schematic symbols against datasheet or external interface specification document (if not yet board proven).
* [x] Schematic symbol matches chosen component package
* [x] Thermal pads are connected to correct power rail (may not always be ground)
* [x] Debug interfaces are not power gated in sleep mode

## Passive components
* [ ] Power/voltage/tolerance ratings specified as required
* [ ] Ceramic capacitors appropriately de-rated for C/V curve
* [ ] Polarized components specified in schematic if using electrolytic caps etc

## Power supply

### System power input

* [ ] Fusing and/or reverse voltage protection at system power inlet
* [ ] Check total input capacitance and add inrush limiter if needed

### Regulators

* [ ] Under/overvoltage protection configured correctly if used
* [ ] Verify estimated power usage per rail against regulator rating
* [ ] Current-sense resistors on power rails after regulator output caps, not in switching loop
* [ ] Remote sense used on low voltage or high current rails
* [ ] Linear regulators are stable with selected output cap ESR
* [ ] Confirm power rail sequencing against device datasheets

### Decoupling
* [ ] Decoupling present for all ICs
* [ ] Decoupling meets/exceeds vendor recommendations if specified
* [ ] Bulk decoupling present at PSU

### General
* [ ] All power inputs fed by correct voltage
* [ ] Check high-power discrete semiconductors and passives to confirm they can handle expected load
* [ ] Analog rails filtered/isolated from digital circuitry as needed

## Signals

### Digital

* [ ] Signals are correct logic level for input pin
* [ ] Pullups on all open-drain outputs
* [ ] Pulldowns on all PECL outputs
* [ ] Termination on all high-speed signals
* [ ] AC coupling caps on gigabit transceivers
* [ ] TX/RX paired correctly for UART, SPI, MGT, etc
* [ ] Differential pair polarity / pairing correct
* [ ] Active high/low enable signal polarity correct
* [ ] I/O banking rules met on FPGAs etc

### Analog

* [ ] RC time constant for attenuators sane given ADC sampling frequency
* [ ] Verify frequency response of RF components across entire operating range. Don't assume a "1-100 MHz" amplifier has the
same gain across the whole range.

### Clocks

* [ ] All oscillators meet required jitter / frequency tolerance. Be extra cautious with MEMS oscillators as these tend to have higher jitter.
* [ ] Correct load caps provided for discrete crystals
* [ ] Crystals only used if IC has an integrated crystal driver
* [ ] Banking / clock capable input rules met for clocks going to FPGAs

### Strap/init pins
* [ ] Pullup/pulldowns on all signals that need defined state at boot
* [ ] Strap pins connected to correct rail for desired state
* [ ] JTAG/ICSP connector provided for all programmable devices
* [ ] Config/boot flash provided for all FPGAs or MPUs without internal flash
* [ ] Reference resistors correct value and reference rail

### External interface protection

* [ ] Power outputs (USB etc) current limited
* [ ] ESD protection on data lines going off board

### Debugging / reworkability

* [ ] Use 0-ohm resistors vs direct hard-wiring for strap pins when possible
* [ ] Provide multiple ground clips/points for scope probes
* [ ] Dedicated ground in close proximity to analog test points
* [ ] Test points on all power rails
* [ ] Test points on interesting signals which may need probing for bringup/debug

## Thermal

* [ ] Power estimates for all large / high power ICs
* [ ] Thermal calculations for all large / high power ICs
* [ ] Specify heatsinks as needed