Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: amaranth-lang/amaranth
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: a295e3599c10
Choose a base ref
...
head repository: amaranth-lang/amaranth
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: dfcf7938eaca
Choose a head ref
  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Feb 4, 2020

  1. hdl.{ast,dsl}: allow whitespace in bit patterns. 

    Fixes #316.
    @whitequark
    whitequark committed Feb 4, 2020
    Copy the full SHA
    dfcf793 View commit details
Showing with 21 additions and 9 deletions.
  1. +6 −4 nmigen/hdl/ast.py
  2. +5 −3 nmigen/hdl/dsl.py
  3. +5 −1 nmigen/test/test_hdl_ast.py
  4. +5 −1 nmigen/test/test_hdl_dsl.py
10 changes: 6 additions & 4 deletions nmigen/hdl/ast.py
View file
Original file line number Diff line number Diff line change
@@ -357,11 +357,12 @@ def matches(self, *patterns):
raise SyntaxError("Match pattern must be an integer, a string, or an enumeration, "
"not {!r}"
.format(pattern))
if isinstance(pattern, str) and any(bit not in "01-" for bit in pattern):
if isinstance(pattern, str) and any(bit not in "01- \t" for bit in pattern):
raise SyntaxError("Match pattern '{}' must consist of 0, 1, and - (don't care) "
"bits"
"bits, and may include whitespace"
.format(pattern))
if isinstance(pattern, str) and len(pattern) != len(self):
if (isinstance(pattern, str) and
len("".join(pattern.split())) != len(self)):
raise SyntaxError("Match pattern '{}' must have the same width as match value "
"(which is {})"
.format(pattern, len(self)))
@@ -372,6 +373,7 @@ def matches(self, *patterns):
SyntaxWarning, stacklevel=3)
continue
if isinstance(pattern, str):
pattern = "".join(pattern.split()) # remove whitespace
mask = int(pattern.replace("0", "1").replace("-", "0"), 2)
pattern = int(pattern.replace("-", "0"), 2)
matches.append((self & mask) == pattern)
@@ -1300,7 +1302,7 @@ def __init__(self, test, cases, *, src_loc=None, src_loc_at=0, case_src_locs={})
new_keys = ()
for key in keys:
if isinstance(key, str):
pass
key = "".join(key.split()) # remove whitespace
elif isinstance(key, int):
key = format(key, "b").rjust(len(self.test), "0")
elif isinstance(key, Enum):
8 changes: 5 additions & 3 deletions nmigen/hdl/dsl.py
View file
Original file line number Diff line number Diff line change
@@ -301,10 +301,12 @@ def Case(self, *patterns):
raise SyntaxError("Case pattern must be an integer, a string, or an enumeration, "
"not {!r}"
.format(pattern))
if isinstance(pattern, str) and any(bit not in "01-" for bit in pattern):
raise SyntaxError("Case pattern '{}' must consist of 0, 1, and - (don't care) bits"
if isinstance(pattern, str) and any(bit not in "01- \t" for bit in pattern):
raise SyntaxError("Case pattern '{}' must consist of 0, 1, and - (don't care) "
"bits, and may include whitespace"
.format(pattern))
if isinstance(pattern, str) and len(pattern) != len(switch_data["test"]):
if (isinstance(pattern, str) and
len("".join(pattern.split())) != len(switch_data["test"])):
raise SyntaxError("Case pattern '{}' must have the same width as switch value "
"(which is {})"
.format(pattern, len(switch_data["test"])))
6 changes: 5 additions & 1 deletion nmigen/test/test_hdl_ast.py
View file
Original file line number Diff line number Diff line change
@@ -464,6 +464,9 @@ def test_matches(self):
self.assertRepr(s.matches("10--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")
self.assertRepr(s.matches("1 0--"), """
(== (& (sig s) (const 4'd12)) (const 4'd8))
""")

def test_matches_enum(self):
s = Signal(SignedEnum)
@@ -484,7 +487,8 @@ def test_matches_width_wrong(self):
def test_matches_bits_wrong(self):
s = Signal(4)
with self.assertRaises(SyntaxError,
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Match pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
s.matches("abc")

def test_matches_pattern_wrong(self):
6 changes: 5 additions & 1 deletion nmigen/test/test_hdl_dsl.py
View file
Original file line number Diff line number Diff line change
@@ -331,12 +331,15 @@ def test_Switch(self):
m.d.comb += self.c1.eq(1)
with m.Case("11--"):
m.d.comb += self.c2.eq(1)
with m.Case("1 0--"):
m.d.comb += self.c2.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(case 11-- (eq (sig c2) (const 1'd1)))
(case 10-- (eq (sig c2) (const 1'd1)))
)
)
""")
@@ -435,7 +438,8 @@ def test_Case_bits_wrong(self):
m = Module()
with m.Switch(self.w1):
with self.assertRaises(SyntaxError,
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits"):
msg="Case pattern 'abc' must consist of 0, 1, and - (don't care) bits, "
"and may include whitespace"):
with m.Case("abc"):
pass