The multiplier is added to Yosys and will soon be released on Github along with other changes

The multiplier is released

@rakeshm75 all the mults macros are also supported in arch-defs

@kgugala, I have pulled the latest code. When I run the design with multiplier, I get the following error:

25.2.2. Analyzing design hierarchy..
ERROR: Module \qlal4s3_mult_cell_macro' referenced in module \AL4S3B_FPGA_IP' in cell `\u_qlal4s3_mult_cell_macro' is not part of the design.
make[3]: *** [quicklogic/tests/quicklogic_testsuite/design3/design3-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_synth.json] Error 1
make[2]: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/file_quicklogic_tests_quicklogic_testsuite_design3_design3-ql-chandalar_ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp_top.eblif.dir/all] Error 2
make[1]: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/design3-ql-chandalar_jlink.dir/rule] Error 2
make: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/design3-ql-chandalar_jlink.dir/rule] Error 2
design3.zip

hi @rakeshm75 I added your test to arch-defs repository antmicro/f4pga-arch-defs@7670933

I ran it and it passes to the bitstream. It looks like you don't have the latest Yosys code. Support for the qlal4s3_mult_cell_macro cell has been added in this commit antmicro@8d691b6

There is one more issue with the design you attached - it get almost entirely optimized out during synthesis.

Hi Karol,

Its the same design which I had filed issue with Yosys that it optimizes the design completely.
The issue number #63 (#63). It was fixed and I could run the design on Yosys, create edif and run through SpDE tool. I have attached the EDF file created by Yosys and Precision for your reference.

We should have only qlal4s3_mult_cell_macro multiplier primitive not qlal4s3_mult_32x32_cell nor qlal4s3_mult_16x16_cell. 32x32 or 16x16 multiplier should be built from the base qlal4s3_mult_cell_macro.

(* blackbox *)
module qlal4s3_mult_cell_macro (
input [31:0] Amult,
input [31:0] Bmult,
input [1:0] Valid_mult,
input sel_mul_32x32,
output [63:0] Cmult );
endmodule

design3_EDF.zip