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Traceback (most recent call last):
File "test.py", line 20, in <module>
print(verilog.convert(m))
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/back/verilog.py", line 76, in convert
rtlil_text = rtlil.convert(*args, **kwargs)
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/back/rtlil.py", line 1017, in convert
fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 533, in prepare
fragment._propagate_ports(ports=(), all_undef_as_ports=True)
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 462, in _propagate_ports
self._prepare_use_def_graph(parent, level, uses, defs, ios, self)
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 436, in _prepare_use_def_graph
subfrag._prepare_use_def_graph(parent, level, uses, defs, ios, top)
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 428, in _prepare_use_def_graph
add_defs(value._lhs_signals())
File "/home/robin/.guix-profile/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 396, in add_defs
assert defs[sig] is self
AssertionError
The problem is, that i.a and i.b were used by the instance as outputs, but in the toplevel module a is assigned to. The error message look similar to #191 but I am not sure this is actually the same bug.
The text was updated successfully, but these errors were encountered:
Executing the following snippet
fails with this rather unclear error message:
The problem is, that
i.a
andi.b
were used by the instance as outputs, but in the toplevel modulea
is assigned to. The error message look similar to #191 but I am not sure this is actually the same bug.The text was updated successfully, but these errors were encountered: