It would be nice to be able to add an internal reset signal to a platform's default clock domains. It looks like you can set default_rst in a board file, but it also looks like that needs to be a platform Resource such as an I/O pin.

In a nutshell, it'd be great if this worked (assuming that the elaborate method also contains some logic that uses m.d.sync so it doesn't get optimized away):

class SomeDesign(Elaboratable):
  def __init__(self):
    self.reset_sig = Signal(1, reset=0b0, reset_less=True)

  def elaborate(self, platform):
    m = Module()
    m.d.comb += m.d.sync.rst.eq(self.reset_sig)
    return m

But that results in an AttributeError: '_ModuleBuilderDomain' object has no attribute 'rst'. It looks like there is also a ResetSignal() function, but I couldn't get that to work either. Maybe I was calling it wrong, the closest I got was:

[...]
def elaborate(self, platform):
  m = Module()
  m.d.comb += ResetSignal(domain="sync").eq(self.clk_rst)
  return m

That returns an AssertionError with the top level of the stack trace pointing here.

It looks like it is possible to re-create the 'sync' domain using the same logic as create_missing_domain, but I had to make a small change to that method to accept an arbitrary reset Signal for this to work:

[...]
def elaborate(self, platform):
  m = Module()
  if platform != None:
    platform.create_missing_domain("sync", reset_sig=self.clk_rst)
  return m

Is there maybe a way to access the global 'sync' instead of trying to modify it from m.domains? Or some other way to do this that I'm not thinking of? Thanks!