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base repository: amaranth-lang/amaranth
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base: 2f8669cad6a2
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head repository: amaranth-lang/amaranth
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compare: 12c79025f3cf
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Mar 12, 2020

  1. vendor: fix a few issues in commit 2f8669c.

    @whitequark
    whitequark committed Mar 12, 2020
    Copy the full SHA
    12c7902 View commit details
Showing with 6 additions and 5 deletions.
  1. +2 −1 nmigen/lib/cdc.py
  2. +1 −1 nmigen/vendor/intel.py
  3. +1 −1 nmigen/vendor/xilinx_7series.py
  4. +1 −1 nmigen/vendor/xilinx_spartan_3_6.py
  5. +1 −1 nmigen/vendor/xilinx_ultrascale.py
3 changes: 2 additions & 1 deletion nmigen/lib/cdc.py
View file
Original file line number Diff line number Diff line change
@@ -127,7 +127,8 @@ def __init__(self, i, o, *, domain="sync", stages=2, async_edge="pos", max_input
self._stages = stages

if async_edge not in ("pos", "neg"):
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not {!r}"
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
"not {!r}"
.format(async_edge))
self._edge = async_edge

2 changes: 1 addition & 1 deletion nmigen/vendor/intel.py
View file
Original file line number Diff line number Diff line change
@@ -403,7 +403,7 @@ def get_ff_sync(self, ff_sync):
def get_async_ff_sync(self, async_ff_sync):
m = Module()
sync_output = Signal()
if async_ff_sync.edge == "pos":
if async_ff_sync._edge == "pos":
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),
2 changes: 1 addition & 1 deletion nmigen/vendor/xilinx_7series.py
View file
Original file line number Diff line number Diff line change
@@ -420,7 +420,7 @@ def get_async_ff_sync(self, async_ff_sync):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)

if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
2 changes: 1 addition & 1 deletion nmigen/vendor/xilinx_spartan_3_6.py
View file
Original file line number Diff line number Diff line change
@@ -451,7 +451,7 @@ def get_async_ff_sync(self, async_ff_sync):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)

if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
2 changes: 1 addition & 1 deletion nmigen/vendor/xilinx_ultrascale.py
View file
Original file line number Diff line number Diff line change
@@ -416,7 +416,7 @@ def get_async_ff_sync(self, async_ff_sync):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)

if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)