-
Notifications
You must be signed in to change notification settings - Fork 112
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
SDC/XDC create_clock and set_false_path constraints should propigate through Yosys #1291
Comments
Yes. We can also do the clock constraint propagation through PLLs and and other boxes here. |
@daveshah1 - FYI this is the direction we are planning on going with constraints with VPR. Do you think it would be useful for nextpnr at all? |
I implemented net aliases in nextpnr, so a constraint in nextpnr can be any of the names that Yosys gives to a net. But this could be useful too |
@daveshah1 How do you figure out the net aliases? |
In the JSON, the netnames section format allows more than one name for each net. I don't know if there is a BLIF equivalent. |
Can you close this issue once this is merged? |
|
All related PRs have been merged. Closing. |
Is there a separate issue so that |
Currently SDC constraints are passed directly to VPR, which means the net names need to be the output net names from Yosys. However, constraints should be specified on the nets in the input verilog, and then a new SDC constraints file should be output from Yosys with the new net names.
Adding this feature to the XDC plugin should work?
@tmichalak / @acomodi I believe this would allow the LiteX XDC constraints to be used throughout the flow?
@mithro FYI
The text was updated successfully, but these errors were encountered: