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xc7 cells_map.v contains illegal verilog constructs now rejected by latest yosys #2020

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Xiretza opened this issue Feb 9, 2021 · 1 comment · Fixed by #2039
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xc7 cells_map.v contains illegal verilog constructs now rejected by latest yosys #2020

Xiretza opened this issue Feb 9, 2021 · 1 comment · Fixed by #2039

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@Xiretza
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Xiretza commented Feb 9, 2021

See YosysHQ/yosys#2579.

An example of this construct can be seen here: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/45c83a2592923b9a785aa05c9464b5f453ebd151/xc/xc7/techmap/cells_map.v#L1140-L1146

I don't know how many more instances of this there are in the codebase, and I don't know what a proper fix for this would look like.
@litghost
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litghost commented Feb 9, 2021 •
edited

I believe it would be legal to convert from if(X) ... to a static mux and some boolean logic because it would not longer be in the generate statement? E.g.:

assign REGCLKA = DOA_REG ? CLKARDCLK : 1b'1;
localparam ZINV_REGCLKARDRCLK = (DOA_REG && !IS_CLKARDCLK_INVERTED);

I think it was more readable as an if inside a generate, but if it's not legal then so it goes.

It sounds like using the hier name (e.g. genblock.param) would also work, but only as an implementation specific extension.

@dnltz dnltz mentioned this issue Feb 18, 2021
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xc7: techmap: Remove localparam from generate blocks dnltz/symbiflow-arch-defs
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@litghost @Xiretza