The largest US+ fabrics like the VU19P fail when writing the FPGA interchange device database because the flat node storage model in the FPGA interchange device database is too memory intensive.

This task is for implementing a routing graph folding scheme (prototype: f4pga/prjxray#1477) into the FPGA interchange device database. Ideally the scheme would allow for online node <-> wire lookup, but this is not required. The only requirement is that node <-> wire lookup not require flatting the entire node scheme to use. The current prjxray and prjuray graph folding schemes (connections.json) do require flatting the entire node scheme, so they are not suitable.

This task can be broadly split into 3 tasks:

• Propose and prototype a graph folding scheme. Test on parts of increasing size. For example, Add example graph folding prototype. f4pga/prjxray#1477 tested on the A50 (~50k LUT), A100T (~100k LUT) and A200T (~200k LUT). Ideally we'd have numbers for a 1000 class (~1000k LUT) and 2000 class (~2000k) parts
• Extend the FPGA interchange device database schema with the new schema (e.g. PR on https://github.com/SymbiFlow/fpga-interchange-schema)
• Implement graph folding into RapidWright during device database write and verify (e.g. PR on https://github.com/xilinx/rapidwright)