>>> from nmigen import Module, Signal
>>> from nmigen.back import verilog, rtlil
>>> m = Module()
>>> s = Signal(1)
>>> m.d.comb += s.eq(1)
>>> print(verilog.convert(m))
(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top();
  reg \initial  = 0;
  (* src = "<stdin>:1" *)
  reg s;
  always @* begin
    if (\initial ) begin end
    s = 1'h0;
    s = 1'h1;
    1'hx = 1'hx;
  end
endmodule

>>> print(rtlil.convert(m))
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "top"
module \top
  attribute \src "<stdin>:1"
  wire width 1 \s
  wire width 1 $verilog_initial_trigger
  process $group_0
    assign \s 1'0
    assign \s 1'1
    assign $verilog_initial_trigger $verilog_initial_trigger
    sync init
      update $verilog_initial_trigger 1'0
  end
end