#
# This file is part of LUNA.
#
# Copyright (c) 2020 Great Scott Gadgets <info@greatscottgadgets.com>
# SPDX-License-Identifier: BSD-3-Clause

""" TinyFPGA Platform definitions.

This is a non-core platform. To use it, you'll need to set your LUNA_PLATFORM variable:

    > export LUNA_PLATFORM="luna.gateware.platform.glasgow:GlasgowPlatform"
"""

import os
import subprocess

from nmigen import Elaboratable, ClockDomain, Module, ClockSignal, Instance, Signal, Const, ResetSignal
from nmigen.build import Resource, Subsignal, Pins, Attrs, Clock, Connector, PinsN
from nmigen_boards.resources import *
from nmigen.vendor.lattice_ice40 import *

from .core import LUNAPlatform


class GlasgowDomainGenerator(Elaboratable):
    """ Creates clock domains for the TinyFPGA Bx. """

    def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
        pass

    def elaborate(self, platform):
        m = Module()
        locked = Signal()

        # Create our domains...
        m.domains.sync   = ClockDomain()
        m.domains.usb    = ClockDomain()
        m.domains.usb_io = ClockDomain()
        m.domains.fast   = ClockDomain()
        # ... create our 48 MHz IO and 12 MHz USB clock...
        # Fout = 48MHz * (47 + 1) / (2^4 * (2 + 1)) = 48MHz
        clk48  = Signal()
        clk12  = Signal()
        m.submodules.pll = Instance("SB_PLL40_2F_CORE",
            i_REFERENCECLK  = platform.request(platform.default_clk),
            i_RESETB        = Const(1),
            i_BYPASS        = Const(0),

            o_PLLOUTCOREA   = clk48,
            o_PLLOUTCOREB   = clk12,
            o_LOCK          = locked,

            # Create a 48 MHz PLL clock...
            p_FEEDBACK_PATH = "SIMPLE",
            p_PLLOUT_SELECT_PORTA = "GENCLK",
            p_PLLOUT_SELECT_PORTB = "SHIFTREG_0deg",
            p_DIVR          = 2,
            p_DIVF          = 47,
            p_DIVQ          = 4,
            p_FILTER_RANGE  = 1,
        )

        # ... and constrain them to their new frequencies.
        platform.add_clock_constraint(clk48, 48e6)
        platform.add_clock_constraint(clk12, 12e6)

        # We'll use our 48MHz clock for everything _except_ the usb domain...
        m.d.comb += [
            ClockSignal("usb")     .eq(clk12),
            ClockSignal("sync")    .eq(clk48),
            ClockSignal("usb_io")  .eq(clk48),
            ClockSignal("fast")    .eq(clk48),

            ResetSignal("usb")     .eq(~locked),
            ResetSignal("sync")    .eq(~locked),
            ResetSignal("usb_io")  .eq(~locked),
            ResetSignal("fast")    .eq(~locked)
        ]
        return m


class GlasgowPlatform(LatticeICE40Platform, LUNAPlatform):
    name                   = "Glasgow"
    clock_domain_generator = GlasgowDomainGenerator
    default_usb_connection = "usb"
    device                 = "iCE40HX8K"
    package                = "BG121"
    default_clk            = "clk48"
    resources   = [
        Resource("clk48", 0, Pins("K6", dir="i"),
                 Clock(48e6), Attrs(IO_STANDARD="SB_LVCMOS")),

        *LEDResources(pins="G9", attrs=Attrs(IO_STANDARD="SB_LVCMOS")),

        DirectUSBResource(0, d_p="H2", d_n="H1", pullup="J2", d_p_oe="C1", d_n_oe="D2", attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
    ]

[700726.097558] usb 2-4.6: new full-speed USB device number 86 using ehci-pci
[700726.215703] usb 2-4.6: New USB device found, idVendor=16d0, idProduct=0f3b, bcdDevice= 0.00
[700726.215707] usb 2-4.6: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[700726.215709] usb 2-4.6: Product: USB-to-serial
[700726.215711] usb 2-4.6: Manufacturer: LUNA
[700726.216029] cdc_acm 2-4.6:1.0: ttyACM1: USB ACM device