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Extra/unused LUTs in output design #48

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mbpeterson70 opened this issue Feb 20, 2021 · 1 comment
Closed

Extra/unused LUTs in output design #48

mbpeterson70 opened this issue Feb 20, 2021 · 1 comment

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@mbpeterson70
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Currently, if any LUT is used in a tile, Fasm2bels creates primitives/cells for every LUT in that tile, even for LUTs that were not used in the original design. When this is the case, a LUT that was originally unused is listed in Fasm2bels' output Verilog file as having its inputs as all "1'b1" and its its O5 and O6 outputs effectively do not drive anything, as seen in the examples below:

// Unused LUT
  (* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
  LUT6_2 #(
    .INIT(64'h0000000000000000)
  ) CLBLL_L_X2Y121_SLICE_X0Y121_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y121_SLICE_X0Y121_BO5),
.O6(CLBLL_L_X2Y121_SLICE_X0Y121_BO6)
  );

// Used LUT
  (* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
  LUT6_2 #(
    .INIT(64'hff55ff55f5f5f5f5)
  ) CLBLL_L_X2Y121_SLICE_X0Y121_ALUT (
.I0(LIOB33_X0Y1_IOB_X0Y1_I),
.I1(1'b1),
.I2(CLBLM_R_X3Y130_SLICE_X2Y130_AQ),
.I3(CLBLM_R_X5Y126_SLICE_X7Y126_BQ),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y121_SLICE_X0Y121_AO5),
.O6(CLBLL_L_X2Y121_SLICE_X0Y121_AO6)
  );

image
Original design

image
Fasm2bels output design

Is there a reason why these unused LUTs are included in Fasm2bels' output? It seems like Fasm2bels could create a cleaner Verilog file if it only included used LUTs.

fasm2bels_output.v.zip

@litghost
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Simply because they are equivalent and cleaning up the output isn't the first priority. You are welcome to submit a patch to clean up the output.

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