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Currently, if any LUT is used in a tile, Fasm2bels creates primitives/cells for every LUT in that tile, even for LUTs that were not used in the original design. When this is the case, a LUT that was originally unused is listed in Fasm2bels' output Verilog file as having its inputs as all "1'b1" and its its O5 and O6 outputs effectively do not drive anything, as seen in the examples below:
Is there a reason why these unused LUTs are included in Fasm2bels' output? It seems like Fasm2bels could create a cleaner Verilog file if it only included used LUTs.
Currently, if any LUT is used in a tile, Fasm2bels creates primitives/cells for every LUT in that tile, even for LUTs that were not used in the original design. When this is the case, a LUT that was originally unused is listed in Fasm2bels' output Verilog file as having its inputs as all "1'b1" and its its O5 and O6 outputs effectively do not drive anything, as seen in the examples below:
Original design
Fasm2bels output design
Is there a reason why these unused LUTs are included in Fasm2bels' output? It seems like Fasm2bels could create a cleaner Verilog file if it only included used LUTs.
fasm2bels_output.v.zip
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