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Need to define timing model data schema #15

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litghost opened this issue Feb 25, 2021 · 1 comment
Open

Need to define timing model data schema #15

litghost opened this issue Feb 25, 2021 · 1 comment

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@litghost
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Currently the FPGA interchange device database lacks timing model data. This new schema should cover defining timing models for both the routing graph (e.g. pip and wire delays) and BELs (setup/hold w.r.t. clock, launch from clock, combinatorial delays). This schema should accomidate multiple timing corners and multiple speed grades.
@litghost litghost added this to To Do in FPGA interchange bootstrapping via automation Feb 25, 2021
@litghost litghost changed the title Need to define timing model data Need to define timing model data schema Feb 25, 2021
@litghost litghost mentioned this issue Mar 29, 2021
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@mkurc-ant mkurc-ant moved this from To Do to In progress in FPGA interchange bootstrapping Apr 21, 2021
@mkurc-ant
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There is a draft PR open with a proposal and discussion around it: #38

@kgugala kgugala removed this from In progress in FPGA interchange bootstrapping Oct 12, 2021
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@litghost @mkurc-ant