Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Need a FPGA interchange to FASM generator #27

Closed
litghost opened this issue Feb 25, 2021 · 5 comments
Closed

Need a FPGA interchange to FASM generator #27

litghost opened this issue Feb 25, 2021 · 5 comments
Assignees
Labels
enhancement New feature or request good first issue Good for newcomers

Comments

@litghost
Copy link
Contributor

Now that a basic P&R flow has been create that directly consumes FPGA interchange logical and physical netlist, there is a need to generate FASM directly from the FPGA interchange logical and physical netlist. Ideally this implementation would be able to target multiple architectures. Initial targets would be Artix7 and Zynq US+, as those are the architecture where there is a complete enough bitstream database and FPGA interchange device database to support those arches.

@litghost
Copy link
Contributor Author

litghost commented Feb 25, 2021

This issue will need to grapple with some of the questions raised in chipsalliance/fpga-interchange-schema#12

Solution to chipsalliance/fpga-interchange-schema#12 will change requirements on this tool.

@acomodi
Copy link
Contributor

acomodi commented Apr 6, 2021

@litghost I am trying to get an initial working implementation for the FASM generator, initially tailored for 7-series, while trying to maintain it generic where possible.

One thing I stumbled upon is the generation of FASM features corresponding to route-thru pseudo PIPs. The problem is that the physical netlist does not have any information on whether a PIP is a pseudo one, (e.g. route-thru the OLOGIC site when there is no real BEL used). This would be relevant information to attach the correct FASM features when this kind of route-thru PIP is used and avoid outputting the route-thru PIP feature, given that it does not really exist. Would it make sense to add to the phys netlist schema an isPseudo field to the PIPs and emit that as well?

@litghost
Copy link
Contributor Author

litghost commented Apr 6, 2021

Would it make sense to add to the phys netlist schema an isPseudo field to the PIPs and emit that as well?

You should be able to consult the DeviceResource schema to figure out pseudo pips. There is still the problem of how to emit the FASM features for the pseudo pips, but for now I'd recommend doing a simple table lookup. Eventually the DeviceResource schema should contain enough information to emit the FASM features by understanding pseudo cell placements, but that is potentially hard, so could be considered out of scope.

Location in DeviceResource to determine if pip is pseudo pip:

https://github.com/SymbiFlow/fpga-interchange-schema/blob/4b3269148653b4e73c1c18c86d3c31d6d29e8453/interchange/DeviceResources.capnp#L223-L230

@acomodi
Copy link
Contributor

acomodi commented Apr 6, 2021

@litghost All right, I thought about getting information from the DeviceResources and the only initial problem I had was related to run-time, but I think I know what was wrong and I should be able to cut the overhead.

kowalewskijan pushed a commit to antmicro/python-fpga-interchange that referenced this issue Apr 26, 2021
…pping

Add note about cell to BEL mapping assumption.
@acomodi
Copy link
Contributor

acomodi commented Jun 16, 2021

An initial version of the FASM generator is already merged and working for both xc7 and nexus. Further improvements and generalizations of the FASM generator can be discussed in follow-up issues. Closing

@acomodi acomodi closed this as completed Jun 16, 2021
FPGA interchange bootstrapping automation moved this from In progress to Done Jun 16, 2021
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request good first issue Good for newcomers
Projects
None yet
Development

No branches or pull requests

2 participants