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Need a FPGA interchange to FASM generator #27
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This issue will need to grapple with some of the questions raised in chipsalliance/fpga-interchange-schema#12 Solution to chipsalliance/fpga-interchange-schema#12 will change requirements on this tool. |
@litghost I am trying to get an initial working implementation for the FASM generator, initially tailored for 7-series, while trying to maintain it generic where possible. One thing I stumbled upon is the generation of FASM features corresponding to route-thru pseudo PIPs. The problem is that the physical netlist does not have any information on whether a PIP is a pseudo one, (e.g. route-thru the OLOGIC site when there is no real BEL used). This would be relevant information to attach the correct FASM features when this kind of route-thru PIP is used and avoid outputting the route-thru PIP feature, given that it does not really exist. Would it make sense to add to the phys netlist schema an |
You should be able to consult the Location in |
@litghost All right, I thought about getting information from the DeviceResources and the only initial problem I had was related to run-time, but I think I know what was wrong and I should be able to cut the overhead. |
…pping Add note about cell to BEL mapping assumption.
An initial version of the FASM generator is already merged and working for both xc7 and nexus. Further improvements and generalizations of the FASM generator can be discussed in follow-up issues. Closing |
Now that a basic P&R flow has been create that directly consumes FPGA interchange logical and physical netlist, there is a need to generate FASM directly from the FPGA interchange logical and physical netlist. Ideally this implementation would be able to target multiple architectures. Initial targets would be Artix7 and Zynq US+, as those are the architecture where there is a complete enough bitstream database and FPGA interchange device database to support those arches.
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