Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Need FPGA device database backend from VPR #566

Open
litghost opened this issue Feb 25, 2021 · 1 comment
Open

Need FPGA device database backend from VPR #566

litghost opened this issue Feb 25, 2021 · 1 comment
Labels
VPR
Projects
FPGA interchange bootstrapping

Comments

@litghost
Copy link

The VPR architecture XML and RR graph should be enough information to generate an FPGA interchange device database.
@litghost litghost added this to To Do in FPGA interchange bootstrapping via automation Feb 25, 2021
@issuelabeler issuelabeler bot added the VPR label Feb 25, 2021
@mkurc-ant
Copy link

mkurc-ant commented Apr 21, 2021 •
edited by unfurl-links bot

One of possible challenges I see here is that a VPR rr graph is flattened and the interchange format requires definition of repeatable tiles. There is a need for a mechanism that would analyze a rr graph and identify repeating patterns of nodes and edges.

This is actually done in the OpenFPGA project which use VPR together with "tileable graph" https://openfpga.readthedocs.io/en/master/#. This is exactly what is needed for the interchange.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
VPR
Projects
FPGA interchange bootstrapping
To Do
Milestone
No milestone
Development

No branches or pull requests
2 participants
@litghost @mkurc-ant