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PLLE2_BASE techmap doesn't match yosys' cells #1991

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Xiretza opened this issue Jan 29, 2021 · 3 comments
Open

PLLE2_BASE techmap doesn't match yosys' cells #1991

Xiretza opened this issue Jan 29, 2021 · 3 comments
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@mkurc-ant

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@Xiretza
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Xiretza commented Jan 29, 2021

yosys cells_xtra.v contains:

    output CLKFBOUT;
    output CLKOUT0;
    output CLKOUT1;
    output CLKOUT2;
    output CLKOUT3;
    output CLKOUT4;
    output CLKOUT5;
    output LOCKED;
    input CLKFBIN;
    input CLKIN1;
    input PWRDWN;
    input RST;

while cells_map.v contains:

input         CLKFBIN,
input         CLKIN,

output        CLKFBOUT,
output        CLKOUT0,
output        CLKOUT1,
output        CLKOUT2,
output        CLKOUT3,
output        CLKOUT4,
output        CLKOUT5,

input         RST,
output        LOCKED

Compared to yosys, CLKIN should be CLKIN1, and the PWRDWN pin is missing - fixing these two makes techmap work. This is the only module I had problems with, I don't know if something similar applies to other modules.
@litghost
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litghost commented Jan 29, 2021 •
edited by unfurl-links bot

Per https://github.com/Xilinx/XilinxUnisimLibrary/blob/1c8e05fd1e9a79ceb8b996a0996674122eed086f/verilog/src/unisims/PLLE2_BASE.v#L37-L48 , I agree that the techmap in https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/techmap/cells_map.v#L4295 is wrong.

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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. - SymbiFlow/symbiflow-arch-defs

@litghost
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@mkurc-ant Can you fix this when you bring in the MMCM support?

@mkurc-ant
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@litghost Sure, I'll take a look into it.

@mkurc-ant mkurc-ant mentioned this issue Feb 4, 2021
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@mkurc-ant mkurc-ant mentioned this issue Aug 27, 2021
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@litghost @Xiretza @mkurc-ant