We are moving to XDC, but some of the old demos were written when only PCF support existed.

Ok, great. What about to specify in symbiflow_synth instead of symbiflow_place? Is it the final destination? (symbiflow_synth?) There, we can specify the timing and place constraints?

I think that is just a mistake?

@acomodi / @kgugala -- Thoughts?

@rodrigomelo9 It actually is expected it to be like that.

• PCF: this type of constraints is only concerning placement of IOs, therefore it is required during symbiflow_place as the placement constraints are read at that step only (and a constraints file tailored for VPR is generated as output)
• XDC: this file can contain different kind of constraints and not only placement ones (e.g. timing, etc). We have a yosys plugin capable of parsing the XDC constraints and save the placement locations of the IOs directly in the eblif, thus not requiring any additional arguments in the symbiflow_place step.

Additionally, XDC and PCF should not be used at the same time and it is better to use XDC, given that they can contain also timing and other constraints.

@acomodi -- This seems incorrect. The XDC should contain the IO placements (as well as other constraints)? Is the problem that we are missing a tool which generates the IO constraints file for VPR from an XDC input?

@mithro This is what is happening, the XDC contains all kinds of constraints including the placement ones. The yosys plugin can read the placement constraints and save them in the eblif, for the io place constraints script to generate the VPR constraint files

@acomodi -- So the PCF file is being generated by the output of Yosys which is then converted into the correct format needed by VPR?

@mithro No. There are two independent flows concerning IO placement constraints, depending on what the user chooses:
XDC flow: yosys parses the file and saves the constraints in the eblif. The placement constraints script will read from the eblif and generate the VPR constraints. No PCF is produced
PCF flow: yosys does nothing concerning placement constraints. The placement constraints script reads the PCF and generates the VPR constraints. (The eblif is read also here, but only to get the top level IO nets)

I think we might have discussed this previously. We should hand in the PCF at the same place we hand in the XDC and then the rest of the flow should be the same.

See chipsalliance/yosys-f4pga-plugins#30 and maybe https://docs.google.com/drawings/d/1r2LXypJF5AD40LfHegml3_fIvPT2jZ3n2OZYW9-9dLU/edit ?

Google Docs

Yosys and Constraints System

Yosys Verilog Design .v Timing Constraints .sdc Creates Cells Annotates Cells Optimizer Cells Cells Cells Cells Cells Renamed Cells Netlist .blif Timing Constraints .sdc From Cells From Annotations Optimizer preserves cell annotations but can eliminate cells and mangle net names Annotations can a...

Thanks. My question was answered, so this issue can be closed if you want (I mean, it seems that @mithro detected another problem, but that is not what this issue was about).

Regards