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Bus indices should (arguably) be signed not unsigned #11

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gatecat opened this issue Feb 24, 2021 · 1 comment
Open

Bus indices should (arguably) be signed not unsigned #11

gatecat opened this issue Feb 24, 2021 · 1 comment

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@gatecat
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gatecat commented Feb 24, 2021

Based on some recent comments in YosysHQ/yosys#2567 it is apparent that negative bus indices are legal Verilog (and occasionally used for the fractional part of fixed point values) and therefore should be representable in the interchange format too. This would mean using a signed integer type for these.
@litghost
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Sure, this make sense.

@litghost litghost added this to To Do in FPGA interchange bootstrapping via automation Feb 25, 2021
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@litghost @gatecat