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How to derive the negative edge from a clock #590

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hellow554 opened this issue Feb 5, 2021 · 4 comments
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How to derive the negative edge from a clock #590

hellow554 opened this issue Feb 5, 2021 · 4 comments
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@hellow554
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hellow554 commented Feb 5, 2021

I have a myhdl background and maybe that's why this seems like a very easy task to me.

in myhdl you can define a elaboratele thing like this (http://docs.myhdl.org/en/latest/manual/reference.html#myhdl.always_seq)

@always_seq(clk.negedge, reset=reset)
def logic():
    self.output = self.input
return logic

I can't seem to find an easy way to do something similar in nmigen, without creating a new clockdomain, registering it in my module (as well as defining a clock source, ...).

I would like to write something like this:

m.d.sync.neg += self.output.eq(self.input)

What is the idiomatic way to do this?

(Ps, if you open the discussion tab, you can easily move an (/this) issue to discussions, so they don't litter the issue tab ;) )

@rroohhh
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rroohhh commented Feb 5, 2021

Currently this is done by creating a new clockdomain, driving it by the inverse of the clocksignal and adding it to your module.

@whitequark
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Yep, creating a new clock domain is the idiomatic way (arguably, it is a new domain--at least if you include the polarity in the control set, which I do). You probably want to drive it with the exact same clock signal though, not the inverse.

@rroohhh
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rroohhh commented Feb 5, 2021

Whoops yes, I completely missed the clk_edge=... argument of ClockDomain, sorry!

@hellow554
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RobertBaruch has exactly this topic covered in his tutorial:

https://github.com/RobertBaruch/nmigen-tutorial/blob/master/3_modules.md#tip-clock-domains-with-the-same-clock-but-different-edges

I should go a read more of him, thanks everybody.

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