You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I can't seem to find an easy way to do something similar in nmigen, without creating a new clockdomain, registering it in my module (as well as defining a clock source, ...).
I would like to write something like this:
m.d.sync.neg += self.output.eq(self.input)
What is the idiomatic way to do this?
(Ps, if you open the discussion tab, you can easily move an (/this) issue to discussions, so they don't litter the issue tab ;) )
The text was updated successfully, but these errors were encountered:
Yep, creating a new clock domain is the idiomatic way (arguably, it is a new domain--at least if you include the polarity in the control set, which I do). You probably want to drive it with the exact same clock signal though, not the inverse.
I have a myhdl background and maybe that's why this seems like a very easy task to me.
in myhdl you can define a elaboratele thing like this (http://docs.myhdl.org/en/latest/manual/reference.html#myhdl.always_seq)
I can't seem to find an easy way to do something similar in nmigen, without creating a new clockdomain, registering it in my module (as well as defining a clock source, ...).
I would like to write something like this:
What is the idiomatic way to do this?
(Ps, if you open the discussion tab, you can easily move an (/this) issue to discussions, so they don't litter the issue tab ;) )
The text was updated successfully, but these errors were encountered: