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FPGA interchange logical netlist GND/VCC cell references should come from device database #21

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litghost opened this issue Feb 16, 2021 · 1 comment
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FPGA interchange logical netlist GND/VCC cell references should come from device database #21

litghost opened this issue Feb 16, 2021 · 1 comment

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@litghost
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The initial implementation of Yosys JSON to FPGA interchange logical netlist has constants for the GND/VCC cells, see https://github.com/SymbiFlow/python-fpga-interchange/blob/5597fcefe8c9e0049184a12cf1a7d5298cce9a97/fpga_interchange/yosys_json.py#L75-L79

These constants should be found from the FPGA interchange device database, but that data is missing from the device database schema at this time.
@litghost
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Fixed in #25

FPGA interchange bootstrapping automation moved this from To Do to Done Feb 25, 2021
kowalewskijan pushed a commit to antmicro/python-fpga-interchange that referenced this issue Apr 26, 2021
@litghost
Merge pull request chipsalliance#21 from clavin-xlnx/remove_tile_pat_idx
e86e676 
Removing tile pattern index for now, resolves Issue chipsalliance#17.
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@litghost