Adding a generated Verilog (or other) source is currently not possible if the license check is being used.

we should mark them as generated or vendored (what linguist calls third party) in the .gitattributes;

• https://github.com/github/linguist/blob/master/docs/overrides.md#generated-code
• https://github.com/github/linguist/blob/master/docs/overrides.md#vendored-code

The license checker should then understand this information.

There should be a way to skip the check for generated files or, alternatively, add the possibility to add an escape line to bypass the check for a given file.

We should not have a way to bypass the license check.

GitHub

github/linguist

Language Savant. If your repository's language is being reported incorrectly, send us a pull request! - github/linguist

GitHub

github/linguist

Language Savant. If your repository's language is being reported incorrectly, send us a pull request! - github/linguist