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Memory ReadPort and WritePort are broken for negedge clockdomains #611

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anuejn opened this issue May 18, 2021 · 0 comments · Fixed by #1039
Closed

Memory ReadPort and WritePort are broken for negedge clockdomains #611

anuejn opened this issue May 18, 2021 · 0 comments · Fixed by #1039
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improvement unsoundness

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@anuejn
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anuejn commented May 18, 2021

Currently, ReadPort and WritePort do not respect the clock polarity of the domain. This makes it impossible to use Memory with negedge domains.

see:
https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L281 https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L177
anuejn added a commit to apertus-open-source-cinema/naps that referenced this issue May 18, 2021
@anuejn
fix SocMemory in combination with JTAG
7f092f7 
a bug in nmigen prevents memory from being used in combination with
negedge clock domains as used in the JTAG code
(amaranth-lang/amaranth#611).
This is fixed now by using a posedge domain for JTAG and manually
invevrting the clock.
whitequark added a commit to whitequark/amaranth that referenced this issue Nov 25, 2023
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
dd543ac 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Nov 25, 2023
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
d132b3a 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Dec 15, 2023
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
11748a1 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
wanda-phi added a commit to wanda-phi/amaranth that referenced this issue Jan 16, 2024
@wanda-phi
hdl.mem: Switch to first-class IR representation for memories.
b94d630 
Fixes amaranth-lang#611.
@wanda-phi wanda-phi mentioned this issue Jan 16, 2024
Merged
github-merge-queue bot pushed a commit that referenced this issue Jan 17, 2024
@wanda-phi @whitequark
hdl.mem: Switch to first-class IR representation for memories.
ae36b59 
Fixes #611.
whitequark added a commit to whitequark/amaranth that referenced this issue Jan 20, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
e4a02ae 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Jan 31, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
a18b0c7 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Jan 31, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
80cf9e3 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Feb 4, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
d73e129 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Feb 5, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
70fe005 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Feb 10, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
6f52a59 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Feb 11, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
0edadf8 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
whitequark added a commit to whitequark/amaranth that referenced this issue Feb 11, 2024
@whitequark @wanda-phi
ir,back.rtlil: new intermediate representation. (WIP)
b407d26 
The new intermediate representation allows performing global analyses
on Amaranth code without lowering it to another representation such as
RTLIL.

This commit also changes the RTLIL builder to use the new IR. This
results in several improvements:
- Memories with negedge clocks are now supported (fixes amaranth-lang#611).
- Reuse of the same `Value` in multiple expressions is now emitted more
  efficiently (fixes amaranth-lang#787).
- Complex expressions on the right-hand side of an assignment are now
  emitted with less use of Python stack space (fixes amaranth-lang#839). WIP
- Complex expressions on the left-hand side of an assignment are now
  emitted more efficiently.

Co-authored-by: Wanda <wanda@phinode.net>
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hdl.mem: Switch to first-class IR representation for memories. wanda-phi/amaranth
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@whitequark @anuejn