- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.

verilog: impose limit on maximum expression width

sv: support for parameters without default values