If we specify the default cell connections then this should be avoidable, as nextpnr should create and connect these ports automatically.

RapidWright isn't currently generating these and I don't think it has data for those, but perhaps this is something that could be added (I demonstrated how Vivado handles this at chipsalliance/fpga-interchange-schema#35 (comment) )

Ok, thanks for the pointers.

In case RW cannot get the required data, I wonder whether it might be a valid (and feasible) solution to patch the device? It may be quite verbose to add a patch for all the cells, but I cannot think of another way of providing this data.