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Slicing a Value with a bool generates invalid RTLIL #601

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jfng opened this issue Mar 17, 2021 · 0 comments
Closed

Slicing a Value with a bool generates invalid RTLIL #601

jfng opened this issue Mar 17, 2021 · 0 comments
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backend:rtlil bug

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@jfng
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jfng commented Mar 17, 2021

Repro:

from nmigen import *
from nmigen.back import rtlil

m = Module()
foo = Signal(2)
m.d.comb += foo[True].eq(1)

print(rtlil.convert(m))

Output:

attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "top"
module \top
  attribute \src "/tmp/repro.py:5"
  wire width 2 \foo
  wire width 1 $verilog_initial_trigger
  process $group_0
    assign \foo 2'00
    assign \foo [True] 1'1
    assign $verilog_initial_trigger $verilog_initial_trigger
    sync init
      update $verilog_initial_trigger 1'0
  end
end

which throws the following Yosys error:

ERROR: Parser error in line 10: syntax error
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@whitequark @jfng