Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

XilinxSpartan6Platform and XilinxSpartan3APlatform support broken on commit 2f8669ca #549

Closed
vmunoz82 opened this issue Nov 21, 2020 · 0 comments
Closed

XilinxSpartan6Platform and XilinxSpartan3APlatform support broken on commit 2f8669ca #549

vmunoz82 opened this issue Nov 21, 2020 · 0 comments
Labels
bug toolchain:ise
Milestone
0.3

Comments

@vmunoz82
Copy link

Hi, thank you for nmigen, I think is really awesome :)

Before commit 2f8669ca, you can test that it worked easily building the default Blinky module:

python3 -m nmigen_boards.atlys

And will build fine.

But after that commit, you got:

Traceback (most recent call last):
  File "/usr/lib/python3.8/runpy.py", line 194, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/usr/lib/python3.8/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "/usr/local/lib/python3.8/dist-packages/nmigen_boards/atlys.py", line 230, in <module>
    AtlysPlatform().build(Blinky(), do_program=True)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/build/plat.py", line 95, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/build/plat.py", line 137, in prepare
    fragment._propagate_domains(self.create_missing_domain, platform=self)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/hdl/ir.py", line 380, in _propagate_domains
    new_domains = self._create_missing_domains(missing_domain, platform=platform)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/hdl/ir.py", line 365, in _create_missing_domains
    new_fragment = Fragment.get(value, platform=platform)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/hdl/dsl.py", line 538, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/lib/cdc.py", line 155, in elaborate
    return platform.get_async_ff_sync(self)
  File "/usr/local/lib/python3.8/dist-packages/nmigen/vendor/xilinx_spartan_3_6.py", line 440, in get_async_ff_sync
    if self._max_input_delay is not None:
AttributeError: 'AtlysPlatform' object has no attribute '_max_input_delay'

Howhever if you comment out the default system clock (on XilinxSpartan6Platform) it build successfully.

class AtlysPlatform(XilinxSpartan6Platform):
    device  = "xc6slx45"
    package = "csg324"
    speed   = "3"

    def __init__(self, *, JP12="2V5", **kwargs):
        super().__init__(**kwargs)

        assert JP12 in ["2V5", "3V3"]
        self._JP12 = JP12
............
    default_clk = "clk100"
    default_rst = "rst" # comment this
    resources   = [
        Resource("rst",    0, PinsN("T15", dir="i"), Attrs(IOSTANDARD=bank2_iostandard)), # RESET
        Resource("clk100", 0, Pins("L15",  dir="i"),
                 Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),                             # GCLK

Thank you!
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
bug toolchain:ise
Milestone
0.3
Development

No branches or pull requests
2 participants
@whitequark @vmunoz82