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Enable FD primitives #1770

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acomodi opened this issue Nov 12, 2020 · 3 comments
Open

Enable FD primitives #1770

acomodi opened this issue Nov 12, 2020 · 3 comments

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@acomodi
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acomodi commented Nov 12, 2020

The latest litex designs do make use of the FD primitives which are non other than FDREs with the CE set to one and the R set to 0.

These primitives currently generate errors in the yosys synth step, as it seems that they are not included in the xilinx/cell_sim.v shared library:

6.2. Analyzing design hierarchy..
ERROR: Module `\FD' referenced in module `\top' in cell `\FD_15' is not part of the design.
Makefile:28: recipe for target 'top.eblif' failed
make: *** [top.eblif] Error 1

This is the FD instantiation in the design:

FD FD_15(                                                                                                                                                                                                                                                                          
    .C(main_ethphy_clkin),                                                                                                                                                                                                                                                         
    .D(builder_liteethphyrgmii_reset6),                                                                                                                                                                                                                                            
    .Q(builder_liteethphyrgmii_reset7)                                                                                                                                                                                                                                             
);
@litghost
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The latest litex designs do make use of the FD primitives which are non other than FDREs with the CE set to one and the R set to 0.

This change should be in yosys, as I believe this is an example of a re-targeting. All re-targeting should be done during synthesis, rather than in P&R.

To confirm this is a re-targetting, in Vivado if you run create_cell -ref FD test, I expect it will report being retargetted to FDRE/

@acomodi
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acomodi commented Nov 12, 2020

@litghost Thanks and yes, the issue seems to be confirmed a re-targetting one:

create_cell -ref FD test
WARNING: [Coretcl 2-1024] Master cell 'FD' is not supported by the current part and has been retargeted to 'FDRE'.

@HackerFoo HackerFoo added this to Blocking in Litex w/Linux on 200T Nov 24, 2020
@HackerFoo HackerFoo moved this from Blocking to Fix Upstream in Litex w/Linux on 200T Nov 24, 2020
@acomodi
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acomodi commented Nov 24, 2020

This has been fixed by techmapping the FD to the FDRE in #1792.

This needs to be temporary, and a proper fix should be implemented.

@kgugala kgugala removed this from Fix Upstream in Litex w/Linux on 200T Sep 3, 2022
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@litghost @acomodi