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base repository: YoWASP/yosys
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base: 066298b0f742
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head repository: YoWASP/yosys
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compare: 025ebc072070
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  • 7 commits
  • 1 file changed
  • 1 contributor

Commits on Nov 8, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 8, 2020
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    5642d17 View commit details

Commits on Nov 11, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 11, 2020
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    1020a2e View commit details

Commits on Nov 17, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 17, 2020
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    acb5cf7 View commit details

Commits on Nov 19, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 19, 2020
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    568afdd View commit details

Commits on Nov 21, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 21, 2020
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    d9ac9a1 View commit details

Commits on Nov 25, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 25, 2020
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    e0d527f View commit details

Commits on Nov 26, 2020

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 26, 2020
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    025ebc0 View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 yosys-src
2 changes: 1 addition & 1 deletion yosys-src
Submodule yosys-src updated 40 files
+12 −3 Makefile
+53 −57 backends/blif/blif.cc
+294 −58 backends/firrtl/firrtl.cc
+26 −6 backends/verilog/verilog_backend.cc
+0 −1 frontends/rtlil/rtlil_lexer.l
+2 −0 kernel/driver.cc
+58 −14 kernel/yosys.cc
+3 −0 kernel/yosys.h
+55 −22 passes/cmds/check.cc
+3 −1 passes/sat/sim.cc
+1 −17 passes/techmap/abc.cc
+1 −12 passes/techmap/abc9_exe.cc
+45 −0 techlibs/gowin/cells_sim.v
+1 −1 techlibs/intel/common/m9k_bb.v
+1 −0 techlibs/nexus/Makefile.inc
+564 −0 techlibs/nexus/cells_sim.v
+9 −9 techlibs/nexus/cells_xtra.py
+0 −241 techlibs/nexus/cells_xtra.v
+79 −0 techlibs/nexus/dsp_map.v
+37 −1 techlibs/nexus/synth_nexus.cc
+34 −12 tests/arch/nexus/mul.ys
+3 −19 tests/arch/nexus/run-test.sh
+66 −10 tests/various/dynamic_part_select.ys
+8 −8 tests/various/dynamic_part_select/forloop_select.v
+5 −4 tests/various/dynamic_part_select/forloop_select_gate.v
+13 −0 tests/various/dynamic_part_select/latch_002.v
+18 −0 tests/various/dynamic_part_select/latch_002_gate.v
+141 −0 tests/various/dynamic_part_select/latch_002_gate_good.v
+12 −0 tests/various/dynamic_part_select/latch_1990.v
+6 −0 tests/various/dynamic_part_select/latch_1990_gate.v
+5 −4 tests/various/dynamic_part_select/multiple_blocking.v
+5 −4 tests/various/dynamic_part_select/multiple_blocking_gate.v
+5 −4 tests/various/dynamic_part_select/nonblocking.v
+5 −4 tests/various/dynamic_part_select/nonblocking_gate.v
+5 −4 tests/various/dynamic_part_select/original.v
+5 −4 tests/various/dynamic_part_select/original_gate.v
+6 −6 tests/various/dynamic_part_select/reset_test.v
+7 −5 tests/various/dynamic_part_select/reset_test_gate.v
+5 −4 tests/various/dynamic_part_select/reversed.v
+5 −4 tests/various/dynamic_part_select/reversed_gate.v