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Here is the TRM link related to clocks: https://www.quicklogic.com/wp-content/uploads/2020/06/QL-S3-Technical-Reference-Manual.pdf#page=88
Table on page 90 (link) provides information about maximum frequencies for FPGA domain.

Currently I can see that the bitstream_to_openocd tool assumes that the divider is always on, so it is not possible for now to achieve frequencies beyond 40MHz (which is max 80MHz divided by minimum divisor: 2). I think it would be nice to have an option to configure higher frequency in future like maximum 72MHz for FPGA domain, to do so we'll need --osc-freq . We can set default osc_freq and osc_div in platform definition thus setting them would be optional in board definition.

or providing a frequency and letting the tools come up with the closest matching divisor.

I agree this is something that is missing in bitstream_to_openocd tool. For now it is a very manual approach if user wants to configure other frequency for FPGA domain than the default one.

Thanks. I've reviewed the EOS S3 clocking and the approach you picked is perfectly fine.