This issue is to keep track of the issue reported here: #1776.

Problem statement

The auto-generated designs, such as litex, present some small variations in the memory initialization of the BRAMs. This causes a small perturbation in the initial conditions of a test, which lead to major changes in the output results.

This problem might not be only related to the BRAM initialization, but to any small changes that are applied to a specific design, but for the sake of this issue description, we will keep the small BRAM initialization changes as the triggering factor for this issue.

This issue covers the sensitivity of the synthesis step which produces two very different eblifs given a small change in the memory initialization values.

Synthesis

The mem.init changes make yosys produce two completely different output eblifs. There are some tests that need to be performed in order to asses whether the two different eblifs represent the same circuit, and it is just a matter of ordering.

• run post_synthesis simulations
• apply sorting to the output blifs

The expected output of the synthesis step would be to have only a small number of lines affected, relative to the BRAM initializations.

Steps to reproduce

1. Get the latest version of symbiflow-arch-defs (991c74f at the moment of writing)
2. Run one of the litex tests as follows:

cd symbiflow-arch-defs
make env
cd build
make minilitex_arty_bit

3. Save all the run results somewhere
4. Go to the minilitex_arty build directory and delete the arty_soc directory.

cd build/xc/xc7/tests/soc/litex/mini && rm -r arty_soc

5. Re-run the minilitex test, which will trigger a new litex-design generation:

make minilitex_arty_eblif

6. Compare the newly generated eblif with the ones saved from the previous run.