When I tried to generate a design.json for kintex7 through minitest, I found that void wires appeared, such as follows:
{ "name": "dout[0]", "node": "INT_R_X23Y95/LH12", "pin": "L25", "type": "out", "wire": "", "wires_outside_roi": [] }, { "name": "dout[1]", "node": "INT_R_X23Y97/LH12", "pin": "M19", "type": "out", "wire": "", "wires_outside_roi": [] } ], "required_features": [ "", "CLK_BUFG_BOT_R_X67Y100.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE", "CLK_BUFG_BOT_R_X67Y100.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED", "CLK_BUFG_BOT_R_X67Y100.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0", "CLK_BUFG_BOT_R_X67Y100.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0", "CLK_BUFG_BOT_R_X67Y100.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
The void wires made the generation of synth_tiles.json failed. How should I deal with them?