Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: amaranth-lang/amaranth
base: 7ea81f5f06be
Choose a base ref
...
head repository: amaranth-lang/amaranth
compare: 892cff059b37
Choose a head ref
  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on May 20, 2020

  1. vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks. 

    If the clock signal is not a top-level port and has aliases, it can
be optimized out, and then the constraint will no longer apply.
To prevent this, make sure the constrained signal is preferred over
any aliases by using the `keep` attribute.

Vivado does not parse attributes like (* keep = 32'd1 *) as valid
even though, AFAICT, they are equivalent to (* keep = 1 *) or simply
(* keep *) per IEEE 1364. To work around this, use the solution we
currently use for Quartus, which is `write_verilog -decimal`.

Fixes #373.
    @whitequark
    whitequark committed May 20, 2020
    Copy the full SHA
    892cff0 View commit details
    Browse the repository at this point in the history