The attached design is created using logic_cell_macro, when I run the design thro Symbiflow I get the following error:

Error 1:
Type: Blif file
File: /adhome/rakeshm/symbiflow-arch-defs/build/quicklogic/tests/quicklogic_testsuite/counter_8bit/counter_8bit-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top.eblif
Line: 129
Message: Failed to find matching architecture model for 'logic_cell_macro'

Load circuit

Load circuit took 0.00 seconds (max_rss 26.2 MiB, delta_rss +0.3 MiB)

The entire flow of VPR took 0.24 seconds (max_rss 26.4 MiB)
make[3]: *** [quicklogic/tests/quicklogic_testsuite/counter_8bit/counter_8bit-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top.net] Error 1
make[2]: *** [quicklogic/tests/quicklogic_testsuite/counter_8bit/CMakeFiles/file_quicklogic_tests_quicklogic_testsuite_counter_8bit_counter_8bit-ql-chandalar_ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp_top.net.dir/all] Error 2
make[1]: *** [quicklogic/tests/quicklogic_testsuite/counter_8bit/CMakeFiles/counter_8bit-ql-chandalar_analysis.dir/rule] Error 2
make: *** [quicklogic/tests/quicklogic_testsuite/counter_8bit/CMakeFiles/counter_8bit-ql-chandalar_analysis.dir/rule] Error 2

counter_8bit.zip