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Test Failure: murax-vivado-yosys-basys3 #168

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HackerFoo opened this issue Jun 23, 2020 · 3 comments
Closed

Test Failure: murax-vivado-yosys-basys3 #168

HackerFoo opened this issue Jun 23, 2020 · 3 comments
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bug Something isn't working designs Related to designs being used to evaluate the performance in the FPGA Tool Perf

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@HackerFoo
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HackerFoo commented Jun 23, 2020 •
edited

https://hydra.vtr.tools/build/837/nixlog/1/tail

ERROR: [DRC INBB-3] Black Box Instances: Cell 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$25243' of type 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$25244/$_DFFSR_PPP_' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC INBB-3] Black Box Instances: Cell 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$25244' of type 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$25244/$_DFFSR_PPP_' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
@HackerFoo HackerFoo added this to Need triage in fpga-tool-perf Jun 23, 2020
@acomodi
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acomodi commented Jun 23, 2020

This is actually working on kokoro CI

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acomodi commented Jun 25, 2020

@HackerFoo What version of yosys is being used in for this test? I think the issue is that, if the latest yosys is used, different yosys flags need to be applied during synthesis.

@mithro mithro added bug Something isn't working designs Related to designs being used to evaluate the performance in the FPGA Tool Perf labels Jun 25, 2020
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@acomodi YosysHQ/yosys@8f1a320

Updating edalize fixed this.

fpga-tool-perf automation moved this from Need triage to Done Jun 26, 2020
@kgugala kgugala removed this from Done in fpga-tool-perf Jan 17, 2022
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