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Test Failure: vexriscv-vivado-yosys-basys3 #169

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HackerFoo opened this issue Jun 23, 2020 · 1 comment
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Test Failure: vexriscv-vivado-yosys-basys3 #169

HackerFoo opened this issue Jun 23, 2020 · 1 comment
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bug Something isn't working designs Related to designs being used to evaluate the performance in the FPGA Tool Perf

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@HackerFoo
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https://hydra.vtr.tools/build/798/nixlog/1/tail

ERROR: [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: dut/$abc$34397$auto$blifparse.cc:498:parse_blif$34967.
@HackerFoo HackerFoo added this to Need triage in fpga-tool-perf Jun 23, 2020
@mithro mithro added bug Something isn't working designs Related to designs being used to evaluate the performance in the FPGA Tool Perf labels Jun 25, 2020
@HackerFoo
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Updating edalize fixed this.

fpga-tool-perf automation moved this from Need triage to Done Jun 26, 2020
@kgugala kgugala removed this from Done in fpga-tool-perf Jan 17, 2022
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