OS_TYPE=Linux CPU_TYPE=x86_64
'name: sphinxcontrib-verilog-diagrams' 'sphinxcontrib-verilog-diagrams'
source /home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/env/conda/bin/activate sphinxcontrib-verilog-diagrams && cd docs; make html
make[1]: Entering directory '/home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/docs'
Running Sphinx v3.1.1
making output directory... done
building [mo]: targets for 0 po files that are out of date
building [html]: targets for 1 source files that are out of date
updating environment: [new config] 1 added, 0 changed, 0 removed
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d4b290>                                                                      
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853dbe5d0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d619d0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d059d0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d1d850>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d05490>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d05410>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853da37d0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853d3bed0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853ccf2d0>
verilog-diagram <sphinxcontrib_verilog_diagrams.VerilogDiagram object at 0x7f6853ccf390>

/home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/docs/index.rst:38: WARNING: Error in "code-block" directive:
maximum 1 argument(s) allowed, 7 supplied.

.. code-block:: python
   extensions = [
      ...,
      'sphinxcontrib_verilog_diagrams',
   ]
/home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/docs/index.rst:84: WARNING: Title underline too short.

Verilog Code Block (with license header)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/docs/index.rst:106: WARNING: Title underline too short.

Verilog Code Block (without license header)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/tim/github/SymbiFlow/sphinxcontrib-verilog-diagrams/docs/index.rst:106: WARNING: Title underline too short.

Verilog Code Block (without license header)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~