There is port miss match in the primitives that are in top_bit.v file and the above mentioned primitive files (@ /symbiflow-arch-defs/quicklogic/primitives).

Can you point me to the primitives files that needs to be used along with top_bit.v (post layout netlist) for running post-layout simulations.

hi @rakeshm75

please use the cells_sim library from Yosys https://github.com/antmicro/yosys/blob/quicklogic-rebased/techlibs/quicklogic/cells_sim.v

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antmicro/yosys

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hi @kgugala ,

primitives in cells_sim.v don't have any provision for timing annotation whereas /symbiflow-arch-defs/quicklogic/primitives has timing constructs emdedded.

Is that work in progress? let us know when would that be available as well as SDF generation.