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Figure out how to skip copyright header in verilog output in rendered Sphinx docs #47

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mithro opened this issue Apr 16, 2020 · 5 comments · Fixed by SymbiFlow/sphinxcontrib-hdl-diagrams#20
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@mithro
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mithro commented Apr 16, 2020

It would be nice to automatically skip the copyright header when displaying the verilog output into the Sphinx documentation.

Currently a verilog file like this;

/*
 * Copyright (C) 2020  The SymbiFlow Authors.
 *
 * Use of this source code is governed by a ISC-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/ISC
 *
 * SPDX-License-Identifier:	ISC
 */

/*
 * `input wire a` should be detected as a clock because of the `(* CLOCK *)`
 * attribute.
 */
(* whitebox *)
module BLOCK(a, b, o);
	(* CLOCK *)
	input wire a;
	input wire b;
	output wire o;
endmodule

You end up with the output which looks like this;
Screenshot from 2020-04-16 10-42-23

This is probably an issue + test needed in https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams

@daniellimws
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I managed to hide it with the :start-after: option of literalinclude as seen in 646d3d2.

@mithro
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mithro commented Apr 23, 2020

@daniellimws - It would be nice if there was a literalinclude like directive that automatically detected the copyright header in the file and added the :start-after: bit automatically. This could probably be done via a similar manner to https://github.com/mithro/sphinxcontrib-session

GitHub
Sphinx extension for displaying console and other sessions. - mithro/sphinxcontrib-session

@daniellimws
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daniellimws commented Apr 23, 2020

@mithro Where would be a good place to implement this directive? Shall I add this feature into https://github.com/mithro/sphinxcontrib-session?

GitHub
Sphinx extension for displaying console and other sessions. - mithro/sphinxcontrib-session

@mithro
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mithro commented Apr 23, 2020

@daniellimws I think as part of sphinxcontrib-verilog-diagrams probably makes some sense? Otherwise maybe we need a new sphinxcontrib-fancyinclude type project?

@daniellimws
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Alright sounds good, I'll add it to sphinxcontrib-verilog-diagrams.

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2 participants