Figure out how to skip copyright header in verilog output in rendered Sphinx docs #47
Description
It would be nice to automatically skip the copyright header when displaying the verilog output into the Sphinx documentation.
Currently a verilog file like this;
/*
* Copyright (C) 2020 The SymbiFlow Authors.
*
* Use of this source code is governed by a ISC-style
* license that can be found in the LICENSE file or at
* https://opensource.org/licenses/ISC
*
* SPDX-License-Identifier: ISC
*/
/*
* `input wire a` should be detected as a clock because of the `(* CLOCK *)`
* attribute.
*/
(* whitebox *)
module BLOCK(a, b, o);
(* CLOCK *)
input wire a;
input wire b;
output wire o;
endmoduleYou end up with the output which looks like this;
This is probably an issue + test needed in https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams
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daniellimws commentedon Apr 17, 2020
I managed to hide it with the
:start-after:option ofliteralincludeas seen in 646d3d2.mithro commentedon Apr 23, 2020
@daniellimws - It would be nice if there was a
literalincludelike directive that automatically detected the copyright header in the file and added the:start-after:bit automatically. This could probably be done via a similar manner to https://github.com/mithro/sphinxcontrib-sessiondaniellimws commentedon Apr 23, 2020
@mithro Where would be a good place to implement this directive? Shall I add this feature into https://github.com/mithro/sphinxcontrib-session?
mithro commentedon Apr 23, 2020
@daniellimws I think as part of
sphinxcontrib-verilog-diagramsprobably makes some sense? Otherwise maybe we need a newsphinxcontrib-fancyincludetype project?daniellimws commentedon Apr 23, 2020
Alright sounds good, I'll add it to
sphinxcontrib-verilog-diagrams.