Branch : Quicklogic : Error during generation of top_bit.v file #1424
Description
We get the following error when running design3-ql-chandalar_bit_v command:
Generating design3-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_bit.v
Traceback (most recent call last):
File "/home/rakeshm/symbiflow-arch-defs/quicklogic/utils/fasm2bels.py", line 554, in
verilog, pcf, qcf = f2b.convert_to_verilog(fasmlines)
File "/home/rakeshm/symbiflow-arch-defs/quicklogic/utils/fasm2bels.py", line 487, in convert_to_verilog
self.resolve_connections()
File "/home/rakeshm/symbiflow-arch-defs/quicklogic/utils/fasm2bels.py", line 406, in resolve_connections
self.resolve_hops()
File "/home/rakeshm/symbiflow-arch-defs/quicklogic/utils/fasm2bels.py", line 388, in resolve_hops
hop = get_name_and_hop(self.designhops[tloc][hop[0]])
KeyError: 'WBs_ADR[2]'
make[3]: *** [quicklogic/tests/quicklogic_testsuite/design3/design3-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/top_bit.v] Error 1
make[2]: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/file_quicklogic_tests_quicklogic_testsuite_design3_design3-ql-chandalar_ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp_top_bit.v.dir/all] Error 2
make[1]: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/design3-ql-chandalar_bit_v.dir/rule] Error 2
make: *** [quicklogic/tests/quicklogic_testsuite/design3/CMakeFiles/design3-ql-chandalar_bit_v.dir/rule] Error 2
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kgugala commentedon Apr 21, 2020
I cannot really reproduce this one. The design is optimized out and I get very simple top_bit.v file. I'll check why the design is optimized out
rakeshm75 commentedon Apr 21, 2020
@kgugala Are you using the attached design (design3.zip) files. I have pulled debug signals (in the attached design) out, now I am able to place and route the design, tool is not optimizing the design. I have attached the design along with eblif, JLINK files. But when I run design3-ql-chandalar_bit_v command I get the above error.
design3_impl.zip
kgugala commentedon Apr 22, 2020
thanks
I also investigated the design and figured out what was causing the problem here. The original code have
pragma attribute preserve_cell trueset on some blocks. This is, I assume, disabling optimization on those in the tool you're using.Yosys does not support those non-standard pragmas, but rather use
(* keep *)attributes. I added the attributes for the modules in this commit antmicro@f277733. This prevents the design to be optimized out.In the latest fasm2bels code this is fixed. Please fetch the newest version
rakeshm75 commentedon Apr 22, 2020
@kgugala Thanks!
This issue is resolved, so closing the issue.