When there is only a single whitebox module inside the verilog, netlistsvg renders the output as just a few random port flags.

For example the following verilog is rendered like follows;

/*
 * `input wire a` should be detected as a clock because of the `(* CLOCK *)`
 * attribute.
 */
(* whitebox *)
module BLOCK(a, b, o);
	(* CLOCK *)
	input wire a;
	input wire b;
	output wire o;
endmodule

This is probably the right rendering if the output is specified as being :flatten: -- but for non-:flatten: the whitebox should be treated like a blackbox.

This is probably an issue + test needed in https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams