Codecov Report

Merging #357 into master will increase coverage by 0.14%.
The diff coverage is 91.66%.

@@            Coverage Diff             @@
##           master     #357      +/-   ##
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+ Coverage   82.36%   82.50%   +0.14%     
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  Files          35       35              
  Lines        5846     5950     +104     
  Branches     1205     1210       +5     
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+ Hits         4815     4909      +94     
- Misses        868      873       +5     
- Partials      163      168       +5     

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Another thing that came to my mind just now is, that we maybe want to somehow mark "things that are somehow a bundle". This would help to implement genlib.record.iter_flat() without the assumption that Record is the only bundle. Do you have any ideas of how to achive that?

This would help to implement genlib.record.iter_flat() without the assumption that Record is the only bundle. Do you have any ideas of how to achive that?

As described elsewhere, I don't think this is a good idea, and nMigen's built-in records will not support iter_flat. (They are still there in nmigen.compat, but only for compatibility.)

okay

To add to this, I think it is important to examine the use cases of iter_flat and see which other mechanism would suit them well. Of course, it is also important to have an escape hatch for those who really want to use their own kind of records in their own codebase, which is why UserValue is there.

But I don't currently see a convincing case for having a core interoperability mechanism for flat iteration.

I have some utility function to measure the size of a Module (/Elaboratable) by synthesizing it with Yosys and pulling some output from the stat command. To generate the rtlil for this, I use a similar function to extract all nMigen Value like things and add them to the io ports.

But maybe this usecase is a bit too unimportant / hacky to be supported ;).

To generate the rtlil for this, I use a similar function to extract all nMigen Value like things and add them to the io ports.

Take a look at the Yosys expose command. It will let you do this without any cooperation from nMigen at all.

ah nice thanks :)

Oh, and although the Yosys expose command is probably the most elegant way to do this, you're not limited to using it; you can convert the Module into a Fragment, and then iterate through stmt._rhs_signals() for every statement. Really, your use case has quite a few ways to solve it, none of which involve iter_flat as a core interoperability mechanism.

Thanks for the PR!