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Add verible's Verilog auto-formatter to the repository #52

@mithro

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@mithro
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We should run the verilog files in this repo through the verible auto-formatter (think clang-format for verible).

Should probably be part of the make format specified in #51

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          Add verible's Verilog auto-formatter to the repository · Issue #52 · chipsalliance/f4pga-v2x