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There are several tests that do have issues when run with the Vivado-Yosys flow.
Example error output with the murax test design:
CRITICAL WARNING: [Project 1-560] Could not resolve non-primitive black box cell '$_DFFSR_PPP_' instantiated as 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$13435'. 2 instances of this cell are unresolved black boxes. [/data/fpga-tool-perf/build/murax_yosys-vivado_xc7_a35tcpg236-1_basys3_xdc_carry-n/murax.edif:20807]
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 80 instances were transformed.
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 80 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command opt_design
Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC INBB-3] Black Box Instances: Cell 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$13435' of type 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$13436/$_DFFSR_PPP_' has undefined contents and
is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC INBB-3] Black Box Instances: Cell 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$13436' of type 'murax/system_uartCtrl/uartCtrl_1/rx/bufferCC_3/$auto$simplemap.cc:467:simplemap_dffsr$13436/$_DFFSR_PPP_' has undefined contents and
is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 2 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
The text was updated successfully, but these errors were encountered:
There are several tests that do have issues when run with the Vivado-Yosys flow.
Example error output with the murax test design:
The text was updated successfully, but these errors were encountered: