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Get fasm2bels to run also for nextpnr bitstreams #159

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acomodi opened this issue Jun 17, 2020 · 1 comment · Fixed by #161
Closed

Get fasm2bels to run also for nextpnr bitstreams #159

acomodi opened this issue Jun 17, 2020 · 1 comment · Fixed by #161

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@acomodi
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acomodi commented Jun 17, 2020

Currently, fasm2bels runs only for VPR generated bitstreams. To have an apples-to-apples comparison of the obtained results, it would be needed to have also nextpnr outputs to run through fasm2bels as well.

@acomodi acomodi added this to To do in fpga-tool-perf Jun 17, 2020
@acomodi acomodi moved this from To do to High Priority in fpga-tool-perf Jun 17, 2020
@acomodi acomodi moved this from High Priority to In progress in fpga-tool-perf Jun 17, 2020
@acomodi
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acomodi commented Jun 17, 2020

#161 Enables fasm2bels for nextpnr.

However, there are errors that show up when running the litex-linux test:

  1. channels.db seems to be incomplete as it miss some wires. In fact, during fasm2bels, this code fails. By using the channels.db from symbiflow arch defs, this issue seems to be solved.
    The problem seems to be related to the BRAM CLKARDCLK wire, need to investigate the problem in more details, as it is possible that there are some missing steps in the creation of the reduced channels.db file.
  2. Some sinks result in being orphan sinks with no source
  3. By temporarily allowing orphan nets to get past the error, the following error shows up during tcl sourcing in Vivado:
ERROR: [Vivado 12-2285] Cannot set LOC property of instance 'CLBLM_L_X8Y107_SLICE_X10Y107_RAM64X1S_C',  for bel B6LUT Conflicting nets for SLICE_X10Y107.B6LUT.WA4
Two net names are: CLBLM_R_X7Y104_SLICE_X8Y104_DQ and CLBLM_L_X8Y107_SLICE_X11Y107_D5Q,  for bel C6LUT Conflicting nets for SLICE_X10Y107.C6LUT.WA4
Two net names are: CLBLM_R_X7Y104_SLICE_X8Y104_DQ and CLBLM_L_X8Y107_SLICE_X11Y107_D5Q
Resolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.

As the resolution says, it may be necessary to get first all the BEL constraints defined and later all the LOC constraints. This would likely double the size of the tcl file and its source run-time.

fpga-tool-perf automation moved this from In progress to Done Jun 17, 2020
@kgugala kgugala removed this from Done in fpga-tool-perf Jan 17, 2022
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