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compare: 101b53dbac0e
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  • 1 commit
  • 17 files changed
  • 1 contributor

Commits on Jun 17, 2020

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    101b53d View commit details
205 changes: 147 additions & 58 deletions boards/MAXWELL/maxwell-main/clocking.sch
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
$Descr A3 16535 11693
encoding utf-8
Sheet 14 15
Sheet 14 16
Title "MAXWELL Main Board"
Date "2020-06-16"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
@@ -18,93 +18,182 @@ L special-azonenberg:LMK04806 U36
U 1 1 5EF9E8C0
P 1800 5100
F 0 "U36" H 2400 9375 50 0000 C CNN
F 1 "LMK04806" H 2400 9284 50 0000 C CNN
F 1 "LMK04806B" H 2400 9284 50 0000 C CNN
F 2 "" H 1800 5100 50 0001 C CNN
F 3 "" H 1800 5100 50 0001 C CNN
1 1800 5100
1 0 0 -1
$EndComp
$Comp
L special-azonenberg:LMK04806 U36
U 2 1 5EFA0009
P 4500 5100
F 0 "U36" H 5075 6875 50 0000 C CNN
F 1 "LMK04806" H 5075 6784 50 0000 C CNN
F 2 "" H 4500 5100 50 0001 C CNN
F 3 "" H 4500 5100 50 0001 C CNN
2 4500 5100
1 0 0 -1
$EndComp
$Comp
L special-azonenberg:LMK04806 U36
U 3 1 5EFA1019
P 6600 5100
F 0 "U36" H 7418 5651 50 0000 L CNN
F 1 "LMK04806" H 7418 5560 50 0000 L CNN
F 2 "" H 6600 5100 50 0001 C CNN
F 3 "" H 6600 5100 50 0001 C CNN
3 6600 5100
P 5150 6400
F 0 "U36" H 5150 7550 50 0000 L CNN
F 1 "LMK04806B" H 5150 7450 50 0000 L CNN
F 2 "" H 5150 6400 50 0001 C CNN
F 3 "" H 5150 6400 50 0001 C CNN
3 5150 6400
1 0 0 -1
$EndComp
$Sheet
S 6900 1450 1050 1500
S 14300 1000 1150 2450
U 5F303230
F0 "Trigger and Reference Inputs" 50
F1 "trigger.sch" 50
F2 "GND" I L 6900 2250 50
F3 "TRIG_IN_P" O L 6900 2000 50
F4 "TRIG_IN_N" O L 6900 2100 50
F5 "REF_IN_P" O L 6900 2400 50
F6 "REF_IN_N" O L 6900 2500 50
F7 "PPS_IN_P" O L 6900 2650 50
F8 "PPS_IN_N" O L 6900 2750 50
F9 "REF_OUT_P" I L 6900 1600 50
F10 "REF_OUT_N" I L 6900 1700 50
F2 "GND" I R 15450 1250 50
F3 "REF_IN_P" O L 14300 1650 50
F4 "REF_IN_N" O L 14300 1750 50
F5 "PPS_IN_P" O L 14300 1950 50
F6 "PPS_IN_N" O L 14300 2050 50
F7 "REF_OUT_P" I L 14300 2250 50
F8 "REF_OUT_N" I L 14300 2350 50
F9 "TRIG_IN_1_P" O L 14300 1050 50
F10 "TRIG_IN_1_N" O L 14300 1150 50
F11 "TRIG_IN_2_P" O L 14300 1350 50
F12 "TRIG_IN_2_N" O L 14300 1450 50
F13 "REF_OUT" I L 14300 2550 50
F14 "5V0" I R 15450 1050 50
F15 "5V0_N" I R 15450 1350 50
F16 "2V5" I R 15450 1150 50
F17 "TRIG_OUT" I L 14300 2750 50
F18 "GTX_TRIG_OUT_P" I L 14300 2950 50
F19 "GTX_TRIG_OUT_N" I L 14300 3050 50
F20 "GPIO_IN_P" O L 14300 3250 50
F21 "GPIO_IN_N" O L 14300 3350 50
$EndSheet
Text HLabel 5050 1500 0 50 Output ~ 0
Text HLabel 3100 1050 2 50 Output ~ 0
S7_CLK_P
Text HLabel 5050 1600 0 50 Output ~ 0
Text HLabel 3100 1150 2 50 Output ~ 0
S7_CLK_N
Text HLabel 5050 1800 0 50 Output ~ 0
Text HLabel 3100 1350 2 50 Output ~ 0
K7_CLK_P
Text HLabel 5050 1900 0 50 Output ~ 0
Text HLabel 3100 1450 2 50 Output ~ 0
K7_CLK_N
Text HLabel 5050 1300 0 50 Output ~ 0
Text HLabel 3100 4050 2 50 Output ~ 0
ETH_REFCLK
Text HLabel 5050 2050 0 50 Output ~ 0
Text HLabel 3100 1950 2 50 Output ~ 0
LA_REFCLK_P
Text HLabel 5050 2150 0 50 Output ~ 0
Text HLabel 3100 2050 2 50 Output ~ 0
LA_REFCLK_N
Text HLabel 5050 2350 0 50 Output ~ 0
Text HLabel 3100 2250 2 50 Output ~ 0
SYNC_CLK_1_P
Text HLabel 5050 2450 0 50 Output ~ 0
Text HLabel 3100 2350 2 50 Output ~ 0
SYNC_CLK_1_N
Text HLabel 5050 2650 0 50 Output ~ 0
Text HLabel 3100 2550 2 50 Output ~ 0
SYNC_CLK_2_P
Text HLabel 5050 2750 0 50 Output ~ 0
Text HLabel 3100 2650 2 50 Output ~ 0
SYNC_CLK_2_N
Text HLabel 5050 2900 0 50 Output ~ 0
Text HLabel 3100 3450 2 50 Output ~ 0
XG_REFCLK_P
Text HLabel 5050 3000 0 50 Output ~ 0
Text HLabel 3100 3550 2 50 Output ~ 0
XG_REFCLK_N
Text HLabel 8700 3250 0 50 Output ~ 0
Text HLabel 14300 1050 0 50 Output ~ 0
EXT_TRIG_1_P
Text HLabel 8700 3350 0 50 Output ~ 0
Text HLabel 14300 1150 0 50 Output ~ 0
EXT_TRIG_1_N
Text HLabel 8700 3550 0 50 Output ~ 0
Text HLabel 14300 1350 0 50 Output ~ 0
EXT_TRIG_2_P
Text HLabel 8700 3650 0 50 Output ~ 0
Text HLabel 14300 1450 0 50 Output ~ 0
EXT_TRIG_2_N
Text HLabel 8700 3850 0 50 Input ~ 0
TRIG_OUT_P
Text HLabel 8700 3950 0 50 Input ~ 0
TRIG_OUT_N
Text HLabel 8700 4150 0 50 Input ~ 0
GTX_TRIG_OUT_P
Text HLabel 8700 4250 0 50 Input ~ 0
GTX_TRIG_OUT_N
Text HLabel 4100 5600 0 50 Output ~ 0
Text HLabel 3100 1650 2 50 Output ~ 0
RAM_CLK_P
Text HLabel 4100 5700 0 50 Output ~ 0
Text HLabel 3100 1750 2 50 Output ~ 0
RAM_CLK_N
Text Notes 850 1150 0 50 ~ 0
10 MHz from OCXO
Text Notes 850 1450 0 50 ~ 0
External ref in
Text Notes 3800 4100 0 50 ~ 0
25 MHz LVCMOS
Text Notes 3800 3500 0 50 ~ 0
156.25 MHz LVDS
Text Notes 3800 1100 0 50 ~ 0
156.25 MHz LVDS
Text Notes 3800 1700 0 50 ~ 0
100 MHz LVDS
Text Notes 3800 2300 0 50 ~ 0
TBD MHz LVDS
Text Label 3100 2850 0 50 ~ 0
REF_OUT_P
Text Label 3100 2950 0 50 ~ 0
REF_OUT_N
Text Notes 3800 2850 0 50 ~ 0
Reference output, default 10 MHz
Text Label 3100 3150 0 50 ~ 0
REF_OUT
$Comp
L special-azonenberg:LMK04806 U36
U 2 1 5EFA0009
P 1800 7000
F 0 "U36" H 1800 8750 50 0000 L CNN
F 1 "LMK04806B" H 1800 8650 50 0000 L CNN
F 2 "" H 1800 7000 50 0001 C CNN
F 3 "" H 1800 7000 50 0001 C CNN
2 1800 7000
1 0 0 -1
$EndComp
Text HLabel 5050 5450 0 50 BiDi ~ 0
PLL_SYNC
Text HLabel 5050 5650 0 50 Input ~ 0
PLL_SPI_LE
Text HLabel 5050 5750 0 50 Input ~ 0
PLL_SPI_CLK
Text HLabel 5050 5850 0 50 Input ~ 0
PLL_SPI_DATA
Text HLabel 5050 6050 0 50 BiDi ~ 0
PLL_STATUS_HOLDOVER
Text HLabel 5050 6150 0 50 BiDi ~ 0
PLL_STATUS_LD
Text HLabel 5050 6250 0 50 BiDi ~ 0
PLL_STATUS_CLKIN0
Text HLabel 5050 6350 0 50 BiDi ~ 0
PLL_STATUS_CLKIN1
Text HLabel 1700 6850 0 50 Output ~ 0
GND
Wire Wire Line
1700 6850 1700 6950
Text Label 14300 2250 2 50 ~ 0
REF_OUT_P
Text Label 14300 2350 2 50 ~ 0
REF_OUT_N
Text Label 14300 2550 2 50 ~ 0
REF_OUT
Text Label 14300 1650 2 50 ~ 0
REF_IN_P
Text Label 14300 1750 2 50 ~ 0
REF_IN_N
Text Label 1050 1950 2 50 ~ 0
REF_IN_P
Text Label 1050 2050 2 50 ~ 0
REF_IN_N
Text HLabel 14300 1950 0 50 Output ~ 0
PPS_IN_P
Text HLabel 14300 2050 0 50 Output ~ 0
PPS_IN_N
Text HLabel 14300 3250 0 50 Output ~ 0
GPIO_IN_P
Text HLabel 14300 3350 0 50 Output ~ 0
GPIO_IN_N
Text HLabel 5550 3850 0 50 Input ~ 0
3V3
Text HLabel 5450 4050 0 50 Input ~ 0
GND
Text HLabel 15450 1050 2 50 Input ~ 0
5V0
Text HLabel 15450 1150 2 50 Input ~ 0
2V5
Text Label 15450 1250 0 50 ~ 0
GND
Text HLabel 14300 2950 0 50 Input ~ 0
GTX_TRIG_OUT_P
Text HLabel 14300 3050 0 50 Input ~ 0
GTX_TRIG_OUT_N
Text HLabel 12850 2800 0 50 Input ~ 0
TRIG_OUT_N
Text HLabel 12850 2700 0 50 Input ~ 0
TRIG_OUT_P
Text HLabel 15450 1350 2 50 Input ~ 0
5V0_N
Text Notes 12350 2950 0 50 ~ 0
Diff to single conversion
$EndSCHEMATC
8 changes: 6 additions & 2 deletions boards/MAXWELL/maxwell-main/fpgasupport.sch
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@ EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 12 15
Sheet 12 16
Title "MAXWELL Main Board"
Date "2020-06-16"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
@@ -1370,4 +1370,8 @@ Wire Wire Line
14800 1600 14550 1600
Wire Wire Line
14800 1800 14550 1800
Text Label 4300 900 2 50 ~ 0
1V8
Wire Wire Line
4300 900 4300 1000
$EndSCHEMATC
4 changes: 2 additions & 2 deletions boards/MAXWELL/maxwell-main/inputs.sch
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 5 15
Sheet 5 16
Title "MAXWELL Main Board"
Date "2020-06-16"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
5 changes: 3 additions & 2 deletions boards/MAXWELL/maxwell-main/iofpga.sch
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 7 15
Sheet 7 16
Title "MAXWELL Main Board"
Date "2020-06-16"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
@@ -936,4 +936,5 @@ Wire Wire Line
5100 2600 5100 2450
Wire Wire Line
5100 2450 5400 2450
NoConn ~ 2450 7550
$EndSCHEMATC
16 changes: 16 additions & 0 deletions boards/MAXWELL/maxwell-main/lcd.sch
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 16
Title "MAXWELL Main Board"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$EndSCHEMATC
4 changes: 2 additions & 2 deletions boards/MAXWELL/maxwell-main/leftpods.sch
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@ EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 10 15
Sheet 10 16
Title "MAXWELL Main Board"
Date "2020-06-16"
Date "2020-06-17"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
36 changes: 36 additions & 0 deletions boards/MAXWELL/maxwell-main/maxwell-main-cache.lib
Original file line number Diff line number Diff line change
@@ -26,6 +26,21 @@ X Ext 2 0 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# analog-azonenberg_ATTEN_RF_PI_SMALL
#
DEF analog-azonenberg_ATTEN_RF_PI_SMALL R 0 40 Y Y 1 F N
F0 "R" -400 -50 60 H V L CNN
F1 "analog-azonenberg_ATTEN_RF_PI_SMALL" 1000 -50 60 H V R CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 0 300 750 0 0 1 0 f
X RF_IN 1 -200 250 200 R 50 50 1 1 P
X RF_OUT 2 950 250 200 L 50 50 1 1 P
X GND 3 -200 50 200 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# analog-azonenberg_LMH7322
#
DEF analog-azonenberg_LMH7322 U 0 40 Y Y 2 L N
@@ -733,6 +748,27 @@ X GND PAD -200 850 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# special-azonenberg_SY89835U
#
DEF special-azonenberg_SY89835U U 0 40 Y Y 1 F N
F0 "U" 0 -50 50 H V L CNN
F1 "special-azonenberg_SY89835U" 0 -150 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S 0 800 700 0 0 1 0 f
X VCC 1 -200 750 200 R 50 50 1 1 W
X IN_P 2 -200 300 200 R 50 50 1 1 I
X IN_N 3 -200 200 200 R 50 50 1 1 I
X GND 4 -200 650 200 R 50 50 1 1 W
X Q1_N 5 900 50 200 L 50 50 1 1 O
X Q1_P 6 900 150 200 L 50 50 1 1 O
X Q0_N 7 900 450 200 L 50 50 1 1 O
X Q0_P 8 900 350 200 L 50 50 1 1 O
X GND PAD -200 550 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# st-azonenberg_STM32F777xx-TFBGA216
#
DEF st-azonenberg_STM32F777xx-TFBGA216 U 0 40 Y Y 13 L N
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