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These are unknown bits reported by bit2fasm when ran on the LiteX (no ethernet) design implemented using vendor tools on the Nexys Video board (Artix7 200T)
Need to check base addresses but they may be related to IOBs. Memory (DDR) interface on Nexys Video operates on SSTL15 IO standard. I don't think that it has been documented yet.
Good news: These bits are related to DSP and MMCM (probably). They were obtained by running the verilog from LiteX as-is so Vivado inferred DSPs and used MMCM. In SymbiFlow we don't infer DSPs (yet) and MMCM can be replaced by a PLL for now.
There seem not to be any unknown bits related to IOBs (need to double-check). This means that SSTL15 IO standard has no additional bits. We just need to add proper tag mapping in techmaps.
These are unknown bits reported by
bit2fasm
when ran on the LiteX (no ethernet) design implemented using vendor tools on the Nexys Video board (Artix7 200T)Need to check base addresses but they may be related to IOBs. Memory (DDR) interface on Nexys Video operates on SSTL15 IO standard. I don't think that it has been documented yet.
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