In the top_bit.v, the RAMFIFO mapping as issues. The vector signals are mapped wronging in the top_bit.v,
The vector signals need to be mapped [msb:lsb] but its mapped [lsb:msb]:
Example (RAMFIFO):
.A1_0({TILE_X1Y1_WBs_ADR[2], ..., TILE_X1Y1_WBs_ADR[10], 1'b0, 1'b0}),
But it should be mapped as:
.WBs_WR_DAT({2'b00, TILE_X1Y1_WBs_ADR[10:2]}),

I have attached the top_bit.v file here.

design3_bit_v.zip