In the top_bit.v, the Multiplier mapping as issues. The vector signals are mapped wronging in the top_bit.v, The vector signals need to be mapped [msb:lsb] but its mapped [lsb:msb]. Also the vector sizes are wrong.

Output port .Cmult is 64 bits, but can see only 31 ports in the top_bit.v

module qlal4s3_mult_cell_macro(
input [31:0] Amult,
input [31:0] Bmult,
input [1:0] Valid_mult,
input sel_mul_32x32,
output [63:0] Cmult);

endmodule

Attached the top_bit.v file.

design3_bit_v.zip